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2013 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)

IEEE sponsors:

  • IEEE Computer Society

Key areas of interest are (but not limited to): Technology trends and the impact on error rates New error mitigation techniques Characterizing the overhead and design complexity of error mitigation techniques Case studies describing the engineering tradeoffs necessary to decide what mitigation technique to apply Experimental data System-level models: derating factors and validation of error models Error handling protocols (higher-level protocols for robust system design)


Conference Details


26 Mar - 27 Mar 2013



Stanford University
Schwab Center
680 Serra St.
Palo Alto, CA, USA


Web site



Vilas Sridharan
90 Central St.
Boxborough MA USA 01719
+1 617-877-3868


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Call for Papers for Conference Authors

Find details for paper and abstract submission.

Abstract submission deadline: 14 Dec 2012

Final submission deadline: 04 Mar 2013

Notification of acceptance date: 02 Feb 2013