We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: resistive memories, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, root cause defects (physical mechanisms and simulations), Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, designing-in reliability (products, circuits, systems, processes), customer product reliability requirements / manufacturer reliability tasks, wafer level reliability tests (test approaches and reliability test structures), reliability modeling and simulation, optoelectronics, and single event upsets.
13 Oct - 17 Oct 2013
Stanford Sierra Conference Center
130 Fallen Leaf Road
El Dorado National Forest
South Lake Tahoe, CA, USA
National Institute of Standards and Technology
100 Bureau Drive, MS 8120
Gaithersburg MD USA 20899
Please see the conference Web site for full details.
Abstract submission deadline: 12 Jul 2013
Final submission deadline: 10 Oct 2013
Notification of acceptance date: 09 Aug 2013