EDS

Technical Briefs

Among the papers presented by TSMC at the annual IEEE International Electron Devices Meeting (IEDM) held in San Francisco in December 2019, one reported that “we started the volume ramp of the enhanced 7 nm technology with EUV insertion in 2019,” and another one announced that the “true 5 nm platform technology is on schedule for high volume production in 1 H 2020… more than ten EUV layers are employed to replace at least 4 times more immersion layers at cut, contact, via and metal line masking steps for process simplification, faster cycle time and better reliability & yields.” Presentation of these two papers signified the entry of the world’s semiconductor manufacturing into the EUV era. At the December 2020 IEDM, TSMC further states in a paper that its “5 nm node presents ∼30% minimum metal pitch scaling through the finest of EUV approaches coupled with innovative barrier/liner, ESL/ELK, and Cu reflow engineering.” A clear example of EUV lithography in high-volume manufacturing (HVM) is the application processor inside every Apple iPhone 12 in the world, fabricated using TSMC’s EUV-enabled 5 nm process.

Apple’s A14 processor, from TechInsights’ presentation at SEMI Industry Strategy Symposium 2021.

Developing EUV lithography for HVM at TSMC started in 2007. Prior to this, EUV had already had a 20+ year history, mostly in research labs in the US, Japan, and Europe, including those at ASML and Cymer—a specialist in lithographic light sources later acquired by ASML, my current employer. Laboratory research demonstrated its superior resolution and concluded that the technology had no showstoppers; it also finalized on the use of 13.5 nm-wavelength extreme-ultraviolet (hence the name EUV) radiation from laser-produced plasma (LPP) of tin as the light source and vacuum-deposited molybdenum-silicon bilayers as the reflective coating for the mirrors making up the imaging optics. While 193 nm immersion lithography, whose development in 2007 was nearly complete, would provide near-term extension of optical lithography, a new lithography technology with much better resolution would be needed in the long term to secure the future of Moore’s Law. With the use of 4x-reduction projection imaging employing the 6-inch square photomask, EUV lithography, though using entirely reflective rather than mainly refractive optics, could be considered an extension of optical lithography and was thus most attractive among the several next-generation lithography technologies being pursued at that time. In fact, ASML by then had decided on EUV as the next-generation technology it would offer to its customers.

The responsibility of developing EUV lithography for HVM at TSMC fell on my shoulders. To identify all the bottlenecks, experiments had to be carried out on the then available EUV exposure tools, called scanners. There were two in the world. Marking the end of the 20+ year research phase of EUV, ASML shipped in 2006 two prototype EUV scanners, called alpha demo tools (ADT), one to a consortium in Albany, New York and the other one to imec in Belgium. Since TSMC was a core partner of imec, I dispatched a researcher there for a long-stay. The imec ADT had a very low throughput and was very often down. However, we saw encouraging images on the few exposed wafers. Under the leadership of then head of R&D (later co-COO of TSMC) Shang-yi Chiang, we ordered a development tool from ASML, model NXE3100, the successor of the ADT. Because the LPP light source was put to use for the first time, its reliability was poor and the source power never went above 10 watts, less than 1/25 of the output power of the current EUV exposure tools. But I was convinced that this would not be the killer roadblock to the project, for the next-generation light source under development in Cymer’s laboratory had already demonstrated an output power several times higher than 10 watts, though only in bursts. The most important thing to scrutinize at that time was the quality of the imaging optics, made by ASML’s partner ZEISS. Although both ADT and NXE3100 had a numerical aperture (NA) of 0.25, the quality of NXE3100’s optics was much improved over that of the ADT, for we could already obtain from it lithographic patterns (see SEM photo below; P stands for the minimum pitch) intended for the 10 nm generation! Besides, the next-generation exposure tool from ASML, the NXE3300, would have an imaging optics with 0.33 NA, meaning even better resolution! Encouraged, and again with Shang-yi’s support, we marched on and ordered the NXE3300 which would arrive at TSMC in 2013. Towards the end of 2012, I was asked by Chairman Morris Chang on the success rate of EUV lithography. I replied “80%.” He said “You are optimistic! So-and-so told me only 50%!” I was indeed being optimistic; but I had my reasons.

ASML knew from the beginning that EUV development was a high-risk and high-reward undertaking, to the degree that its competitors never planned to develop this technology for HVM. The president of one ASML competitor said to me, “EUV will not work and ASML will have lost all its development money.” It was quite normal to hold this view at that time. But I knew that ASML had the best chance to succeed. First, ASML went all in, investing the substantial resources the project demanded. Second, CTO Martin van den Brink was on top of this technology to the minutest detail. Third, co-development with future users of this technology like TSMC both spread risk and increased resources and drive. For its part, TSMC also directed its resources to maximize its chance of success. Our EUV effort was guided by Shang-yi, with full support from the chairman. As for me, I put my whole heart into developing the technology. Every day I donned my bunny suit and went into the clean room to spend time with my scanners. I was told that I was the only director-level person at TSMC who entered the clean room every day, not sure whether such a remark was meant as a compliment. But I knew that I could not give orders from my office or meeting rooms; I had to see the machine in order to assess whether to stop it for a new experiment or let it continue to run so that more wafers could be exposed on that day, based on its prevalent condition. To speed up development, we carried out joint development with ASML: many experiments were carried out on TSMC’s NXE3300, after initial trials in the Netherlands or the US.

On the road to EUV HVM, the biggest fear in people’s mind was the inability to eventually attain the 250 watt output power from the light source, which was required for a reasonable throughput of these expensive scanners. TSMC’s first NXE3300 had its first light at the end of October 2013. I mentioned above that the most important aspect was the resolution of the imaging optics; this was no longer an issue by then. And we turned our focus to the source power. For some time, we struggled with no more than 10 watts. But continued experiments led us to 40 watts by the spring of 2014. Further experimentation could not lead to higher power: power could be made higher but stability suffered. For the entire summer of 2014, we carried out experiment after experiment in Hsinchu, the Netherlands, and the US.

EUV light is generated by LPP in the source vessel, at one focus of the 0.65m-diameter ellipsoidal collector mirror—the most important component in the vessel. Light is then directed to the mirror’s other focus where a very small opening lets it into the scanner proper. To maintain the EUV output power, the mirror has to be kept clean from tin debris and vapor that is generated by the laser zapping of molten tin droplets, 50,000 times per second, which can quickly contaminate the mirror’s surface and reduce its reflectivity. The billion-dollar game was to find the optimal operating condition to minimize tin contamination of the collector mirror at the highest possible stable output power. The interplay of the laser power, gas pressure, gas flow and hardware configuration around the mirror determined how high the stable EUV output power you could have for the scanner. Here is the chemistry behind it: atomic hydrogen is produced by EUV irradiating the molecular hydrogen gas introduced into the space around the collector mirror; the reactive atomic hydrogen then removes the tin deposited on the mirror’s surface by forming with it the gaseous tin hydride that is pumped out of the vessel. So the idea is to use EUV generated by tin to clean up the mess left by tin!

The watershed moment came on an evening in October 2014, I went into the clean room after a quick meal in TSMC’s cafeteria to meet up with my people and an ASML team led by Bruno La Fontaine for a joint experiment, using the latest set of parameters coming from Cymer in San Diego. With real-time fine adjustments, the digital readout of the power meter continued to climb, steadily. By 9 pm, we reached 90 watts of output power. I immediately realized: EUV HVM would be a success. Why? From 90 watts to 250 watts, the multiplication factor was less than 3, while we had managed to climb from 10 watts to 90 watts, a multiplication factor of 9! Walking out of the clean room towards the gowning area, I sighed and felt euphoric. I will not forget this event for the rest of my life.

I asked for more resources to continue my development of EUV lithography. The senior VP replied, “500 wafers a day! I want to see 500 wafers per day from your machine for a month before giving you more resources!” Though emotional, this was a fair request, as the 90 watt power output had to translate to a sustainable tool throughput. I pow wowed with Frits van Hout who at the time led ASML’s EUV business unit. We decided to tackle the main roadblock: frequent scheduled machine downs in order to replace emptied tin droplet generator and fogged (with tin) collector mirror and the ensuing alignment of their replacements; to get to 500 wafer exposures per day, we had to minimize the frequencies of these replacements. We formed the so-called One Team of ASML and TSMC engineers, worked day and night, and finally succeeded in implementing a new tin droplet generator along with a new algorithm for the laser bombardment, halving the volume of every tin droplet that shot out while not losing the EUV energy it generated. With only 50% of tin consumption in every bombardment, the new droplet generator solved the problems of too-frequent droplet generator replacement and aggravated mirror contamination at the same time, and achieved 500 wafer exposures per day on average for a consecutive 4-week period in the second quarter of 2015.

Thereafter, One Team made continual improvements on many fronts, including further extension of the collector mirror’s lifetime by carrying out many rounds of experiments with improved operating parameters. I want to thank the many ASML colleagues with whom I worked closely throughout my years at TSMC as the leader of EUV development.

EUV lithography has so far been semiconductor industry’s biggest technology development program. To ensure its success, TSMC, Intel, and Samsung together gave ASML over €1 B of R&D money in ensuing five years starting 2013. For itself, ASML acquired Cymer in 2012 for $2.5 B, and paid €1 B to acquire 25% of ZEISS SMT in 2016 and promised to provide it with €760 M of R&D money in the next six years. All this was to ensure the success of EUV lithography.

But EUV lithography is more than just the scanner, it also requires a dedicated infrastructure including, among other components, photoresist and photomask. In fact, photomask itself is a sub-ecosystem. By then, resists for 193 nm lithography based on the mechanism of chemical amplification were quite mature and the same technology could be extended to formulate EUV resists. However, resist suppliers soon realized that EUV HVM could not happen in the next couple of years and became hesitant to direct resources to the development of EUV resists, except JSR, supported by its visionary president Nobu Koshiba. With JSR, we carried out a long-term collaboration that ensured the supply of quality EUV resists to my scanners for years, for which I am very grateful.

Developing masks for EUV lithography at TSMC was also my responsibility. For the multilayer reflective mask blanks, we worked closely with Hoya, whose blanks had many defects in the beginning. Nonetheless, Junichi Horikawa, director of Hoya’s mask blanks business, asked us to purchase a fixed number of blanks per month in order to maintain his mini-production line of EUV blanks. We agreed to his request, for otherwise we would only get mask blanks produced in a laboratory environment! In order to identify and locate these defects accurately, we worked with KLA’s engineers to adapt one of its 193 nm mask inspection tools to the exclusive inspection of defects in mask blanks. Once this tool became available, we were able to give constant feedback to Hoya’s engineers every time we received a new batch of blanks so that processing parameters could be adjusted and improvements made on the next batch. We also worked closely with Gudeng to develop the dual-pod, the special storage case for EUV masks to keep them clean, and with Holon to adapt its mask SEM for elemental identification of mask fall-on defects. In 2011, TSMC became members of SEMATECH (for the second time) in the US and EIDEC in Japan which were dedicated to the development of the EUV infrastructure. EUV aerial-image measurement (AIMS) tool and actinic mask blank inspection tool were specific pieces of equipment whose development was supported by funds from the member companies of these consortia.

Developing EUV for HVM consists of developing the scanner, the infrastructure, and the lithography processing technology. Although this article tries to recount my personal journey with EUV, credits should go to all hard-working members of my former team at TSMC, tenacious colleagues at ASML, ZEISS, and Cymer, R&D colleagues at other semiconductor companies, relevant consortia and research institutes, imec, all the suppliers in this ecosystem, and the supportive top management in these organizations. This was a grand joint effort. But to make the EUV technology successful, this was our one and only choice. At the 2015 SPIE Advanced Lithography symposium, a question came from the audience, “What’s your plan B?” “There is no plan B!” I replied, for I already had confidence that our plan A would succeed.

With 20+ years of research and 12+ years of intensive development, EUV lithography finally succeeded in its adoption in HVM. Moore’s Law was saved. Otherwise, the roadmap of logic semiconductor technology would have ended at the HVM of the 7 nm generation, in 2018. Instead, we are seeing the HVM of the 6 nm and 5 nm technology generations, and CC Wei, the present CEO of TSMC, announced in Q3 of 2020 that the 3 nm generation would be in HVM in the second half of 2022.

Just as 193 nm immersion lithography extended Moore’s Law by ten years (five generations of integrated circuit technology), EUV lithography, with the next-generation 0.55 NA scanner already under development, is set to extend it by at least another ten years. By then, the world’s semiconductor industry will be churning out chips beyond the 1 nanometer technology generation.

Anthony Yen is Vice President and Head of Technology Development Center at ASML. He was with TSMC and led its development of EUV lithography for HVM prior to joining ASML. He did his undergraduate studies in electrical engineering at Purdue University and his graduate studies at MIT, earning his master’s, engineer’s, doctoral, and MBA degrees there. He is a fellow of the IEEE and SPIE.

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