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2001
EDS J.J. Ebers Award
The 2001 J. J. Ebers Award, the prestigious
Electron Devices Society award for outstanding technical contributions
to electron devices, was presented to Dr. Hiroshi Iwai of Tokyo
Institute of Technology at the International Electron Devices
Meeting in Washington, D.C. on 3 December 2001. This award recognizes
Dr. Iwai “For sustained leadership and technical contributions
to the continuous scaling of CMOS devices.” Hiroshi Iwai was born in Tokyo, Japan, in
1949. He received the B.S.and Ph.D. degrees in electronic engineering
from the University of Tokyo, in 1972 and 1992, respectively.
In 1973, he joined the Research and Development Center of Toshiba
Corporation, where he developed the first generation of Toshiba’s
NMOS LSI. From 1977 to 1979, he was also associated with NEC-Toshiba
Information Systems as a research member of advanced NMOS technology.
From 1979 to 1989 he was with the Semiconductor Device Engineering
Laboratory in the Semiconductor Group of Toshiba, where he engaged
in the development of various LSI technologies and products as
a deputy manager — DRAM, SRAM, high-speed logic CMOS, and
mixed analog and logic BiCMOS. In 1983 and 1984, he joined the
Integrated Circuit Laboratory, Stanford University as a Visiting
Scholar, where he studied small-geometry effects of MOSFET capacitances.
From 1989 to 1996, he was associated with the ULSI Research Laboratories
Toshiba as a senior research scientist, heading groups of sub-50
nm CMOS research and ultra-high speed bipolar device development.
From 1997 to March 1999, he was a chief specialist of the Microelectronics
Engineering Laboratories of Toshiba, serving as the project leader
of next generation Si RF technology development of Semiconductor
Group in Toshiba. Since April of 1999, he has been a professor
of the Interdisciplinary Graduate School of Science and Engineering,
Tokyo Institute of Technology, engaging in research on CMOS downsizing. Dr. Iwai contributed to the development of
advanced LSI products in Toshiba for more than 25 years, starting
from a 1k bit NMOS static memory. He has also been a key contributor
to technologies related to the downward scaling of NMOS/CMOS devices
from 8 micrometers to sub-50 nanometer generations. From the late
70’s to the beginning of 90’s, he and his group published
numerous seminal papers on subjects such as the first 2D analysis
of subthreshold-leakage suppression by deep-channel implantation
in 1978, the first demonstration of LOCOS downsizing limits in
1980, invention of on-chip capacitance measurement in 1980, first
demonstration of short- and narrow-channel effects on MOSFET capacitances
in 1984, discovery of avalanche hot-hole injection in p-MOSFETS
in 1988, first systematic study of TED during RTA in 1989, first
demonstration of boron penetration suppression by RTN nitrided-oxide
in 1990, and invention of a unique charge pumping method for fixed
charge spatial distribution in 1991. Dr. Iwai was the first to breakthrough the
50 nm technological wall of down scaling. He and his group established
fundamental technologies for sub-50 nm devices, and demonstrated
a good operation of sub-50 nm MOSFETs in the early 90’s.
The impact of the sub-50 nm MOSFETs drove the SIA roadmaps into
the sub-50 nm region, which had been believed to be very difficult
or even impossible because of limits to further scaling of MOSFET
parameters such as gate oxide thickness. Examples of the ground-breaking
work of Dr. Iwai and his group are: nickel mono salicide MOSFETs
in 1990, 10 nm depth S/D junctions by SSD in 1993, 40 nm gate
length MOSFETs in 1993, epitaxial channel MOSFETs in 1993, direct-tunneling
gate oxide MOSFETs in 1994, and raised S/D MOSFETs using silicon
gate sidewall in 1995. The above structures and techniques, some
of which are fundamental elements of recent 30 — 20 nm MOSFETs,
were originally proposed by him and his group, and were presented
at conferences in the 90’s for the first time. Further, he and his group started RF CMOS
technology development in 1993 and demonstrated various excellent
RF characteristics, such as 150 GHz fT in 1996 and 0.3 dB NF values
in 1998. This led to new applications and markets for RF-CMOS
technologies for wireless telecommunication by international joint
development of RF front-end circuits with designers from universities
and industry. He has contributed to the IEEE EDS, serving
as chair and committee member of many conferences, editor of journals
and newsletters, and an elected member and a standing committee
chair of the IEEE EDS AdCom. His honors include the Nagoya Mayor
Award (1968) at high school graduation, Local Commendation for
Invention from the Japan Institute of Invention and Innovation
(1990) for self-aligned contact hole technology, Grand Prize of
Nikkei BP Technology Awards (1994) for 40 nm MOSFETs, IEEE EDS
Paul Rappaport Award (1994) for his paper on a new charge pumping
technique, IEEE Fellow (1997) for contribution to small geometry
CMOS and BiCMOS, and the IEICE ES Electronics Award (1998) for
research of downsizing Si-MOSFETs. Louis C. Parrillo |
