DL Report from the ED/SSC Bangalore Chapter
The formal inaguration of the IEEE ED/SSC society Bangalore chapter was held on March 16th 2002 at the Indian Institute of Science Bangalore. The event was co-sponsored by the ECE Department, IISc Bangalore. On this occasion a one day workshop titled “Future Challenges in the Deep Sub-Micron Era” was also conducted. The workshop had five invited seminars by the experts in devices and circuits. Prof. Hiroshi Iwai from Tokyo Institute of Technology gave an excellent introduction on “Silicon technology scaling trend from millimeter to nanometer”. The other seminar topics were “Impact of Advanced Process Modules on Low Frequency Noise in CMOS Technology” by Prof. Cor Claeys IMEC Belgium; “Silicon On Insulator Devices for Analog Applications” by Prof. J. Vasi, IIT Bombay; “Designing Reset Systems for Mixed Signal VLSI” by Mr. Rajat Gupta, Cypress Semiconductors Bangalore; “Building in Reliability for Deep Sub-Micron Devices” by Dr. Radhakrishnan, Phillips, Singapore. The workshop received an extremely good response with about 130 individuals from both industry and academia.
J.Vasi, C.Claeys, N. Bhat, H.Iwai, M.K.Radhakrishnan,
K.Rajagopal and Mahesh Patil
at the one day workshop organized by ED/SSC Bangalore chapter
on March 16th
Earlier this year, the chapter had arranged three technical talks. The first two lectures were conducted by Dr. Vishwani Agrawal, Agere Systems, USA on January 16th. The topics were “Delay Testing in Digital Circuits” and “High Speed VLSI Testing with Slow Test Equipment”. These two talks were co-sponsored by Texas Instruments Banagalore. On March 1st, Prof. Q.J. Zhang, Carleton University, Canada gave a lecture on “High Frequency Electronics Design: Towards Next Generation”.