IEDM Short Courses on Videotape

 

The 2001 IEEE International Electron Devices Meeting was held this past year in Washington, DC. The two short courses that were offered at this meeting were titled, “Process and Device Technology for Sub-70 nm CMOS “ and “ Advanced Memory Technology and Architecture.” These short courses are now available on videotape to purchase through IEEE Customer Service.

 

Process and Device Technology for Sub-70 nm CMOS

Presented by Suresh Venkatesan, Motorola; Yuan Taur, IBM; Dr. Luc Van den Hove, IMEC; Dr. Hsing-Huang Tseng, Motorola; Liang-Kai (Kevin) Han, TSMC; Chris J. McDonald, Intel Corporation.

Moore’s Law inexorably drives the density, size and performance of semiconductors. The feature size of modern silicon technology is at the 130nm node and will soon move to the 100nm node. Prognostications of fundamental limits notwithstanding, device gate lengths will shrink down to 50nm in the 100nm node and equivalent gate oxide thickness will scale below 15A. Further shrinking to the 70nm CMOS technology node in many ways places us at crossroads, and each path is fraught with significant challenges. Maintaining performance trends in sub-50 nm devices will drive novel device architectures such as SOI, SiGe, and vertical devices. Increasing gate leakage currents accompanying the aggressive scaling of gate dielectrics coupled with the low power requirements of mobile products will require new gate dielectrics. The wavelength of light will need to be dialed back another notch to keep up with pattern resolution requirements. This course will provide insight into these challenges in the front-end-of-the-line, and discuss potential solutions in the areas of device design, lithography, gate stack, process integration and manufacturing trends.

The first lecture will cover device scaling trends for both low power and high performance applications. It will further cover the device requirements and architectures for the 70nm node including a glimpse at novel structures. The second lecture will cover lithography requirements and trends including a discussion of 157nm lithography systems and beyond. The third lecture will present an overview of the materials under consideration to replace the conventional polysilicon/SiO2 (SiON) system and the process integration challenges spawned by this transition. New materials and process integration challenges for device isolation, shallow junction formation and the silicide technology required for contacting the shallow junctions will be discussed in detail in the fourth lecture. Finally, not all trends are benefited by the performance and cost driven scaling paradigm. Yield enhancement in particular is made more challenging by the shrinking dimensions. Requirements and trends for efficient manufacturing and yield management will be the topic of the final lecture.

Order information:

Title: Process and Device Technology for Sub-70 nm CMOS
NTSC Order No. EV6983
NTSC ISBN 0-7803-6836-3
PAL Order No. EV6984 PAL ISBN 0-7803-6837-1
IEEE Member Price: $380.00
List Price: $450.00

 

Advanced Memory Technology and Architecture

Presented by Kunio Nakamura, NEC Corporation; Clair Webb, Intel Corporation; Won-Seong Lee, Samsung Electronics; Kenji Noda, NEC Corporation; Raffaele Zambrano, STMicroelectronics; Saied Tehrani, Motorola Inc.

The explosive evolution of digital information technologies requires innovation not only in logic devices but also in the semiconductor memory systems. For example, next generation cellular phones will need much larger memory capacity for digital signal processing than present systems, the use of DRAM cache can reduce MPU power, and, in the distant future, main memory may be substituted by high density non-volatile memory.

Under these IT market needs, continuing efforts in process and circuit technologies have led to realization of commercially available Giga-bits DRAM within a few years. Performance improvement towards higher bandwidth also continues in SDRAM or RDRAM, adopting the novel system architectures to cope with aggressively increasing MPU operation frequency. Embedded DRAM with high bandwidth and low latency has already been introduced for graphic applications. In SRAM, high speed cache with the operating speed over 1 GHz has been developed with deep sub-micron technology. Power management is also an important issue, especially for the SRAM used in mobile applications.

Recently, the non-volatile memory market has been growing much more rapidly than other fields, thanks to the growth of portable multimedia devices. The NAND flash memory for mass data storage, the NOR flash memory for stand-alone and embedded applications, and the EEPROM for the smart card have been leading the market. These devices, however, have programming speed and endurance limitation. To overcome these drawbacks, development of the emerging technologies such as FeRAM or non-volatile magnetoresistive RAM (MRAM) is in progress.

This course starts with an overview of the MPU architecture evolution and its influence on memory architecture. The second lecture presents the leading edge process and device technologies for Giga-bits DRAM. The third lecture describes state-of-the-art SRAM device and circuit technologies. The fourth lecture deals with non-volatile memory, and the appropriate device solution for each application will be discussed. The final lecture shows potential of MRAM device as a promising candidate of the future non-volatile memory.

Order information:

Title: Advanced Memory Technology and Architecture
NTSC Order No. EV6985
NTSC ISBN 0-7803-6838-X
PAL Order No. EV6986 PAL ISBN 0-7803-6839-8
IEEE Member Price: $380.00
List Price: $450.00

Here’s how to place your order for the above videos:

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Fax: (732) 981-9667
Online: http://shop.ieee.org/store
Email: customer.service@ieee.org