Status Report from the 2001 Graduate Student Fellowship Winners
In 2000, the IEEE approved the establishment of the Electron Devices Society Graduate Student Fellowship Program. The Program is designed to promote, recognize, and support graduate level study and research within the Electron Devices Society’s fields of interest: which include: Compact Modeling, Compound Semiconductor Devices and Circuits, Device Reliability Physics, Displays, Electronic Materials, Microelectromechanical Systems, Nanotechnology, Optoelectronic Devices, Photovoltaic Devices, Power Devices and ICs, Semiconductor Manufacturing, Technology Computer-Aided Design, Vacuum Devices, and VLSI Technology and Circuits. In deference to the increasing globalization of our Society, at least one fellowship is to be awarded to students in each of three geographical regions: Americas, Europe/Mid-East/Africa, and Asia-Pacific.
In July 2001, EDS announced the first winners of the Fellowship awards. The three winners are: T.K. Ghosh of Lancaster University in the United Kingdom, Sergei Kucheyev of the Australian National University, and Yee-Chia Yeo of the University of California, Berkeley. The winners are pursuing distinctly different research topics for their doctoral degrees. The following are brief progress reports on the activities of the winners.
Yee-Chia
Yeo is a student in the Department of Electrical and Computer
Engineering at the University of California, Berkeley and his
supervisor is Professor Chenming Hu.
Yee-Chia Yeo’s research interests are related to semiconductor devices and electronic materials, with focus on front-end issues in complementary metal-oxide-semiconductor (CMOS) device technology. He has previously conducted research on solid-state physics and optoelectronic devices. Currently, he works on the design, fabrication, characterization, and modeling of CMOS transistors, with specific engagement on the diverse challenges faced in device scaling for improved performance and density of integrated circuits. Issues addressed in his recent projects include: channel engineering using novel materials such as silicon-germanium (SiGe), novel device structures such as the ultra-thin-body transistor, alternative gate dielectrics for reduction of direct tunneling gate leakage current, and CMOS process integration involving a dual-metal gate technology. His research encompasses experimental device fabrication and process development, as well as theoretical modeling of materials interfaces and device simulation.
In his work on strained-channel transistors, he developed a simple and novel bulk CMOS process that integrates a pseudomorphically-strained SiGe channel layer for transistor performance enhancement. He has also worked on the integration of the SiGe heterostructure channel in a novel device structure, the ultra-thin-body MOS transistor. The ultra-thin-body transistor relies on a body thickness of 20 nm or thinner to suppress short-channel effects. Some highlights of this project were the demonstration of the first ultra-thin-body MOS transistor incorporating a SiGe heterostructure channel, and the report of the smallest heterostructure MOS transistor to date. The ultra-thin-body was formed by a novel solid-phase epitaxy technique. From June 2001 – January 2002, he was with the Exploratory Technology Department of Taiwan Semiconductor Manufacturing Company, Taiwan, where he led a team of engineers on strained-channel MOS transistors research and development.
Another area of his research relates to alternative gate dielectrics and metal gates, their process integration issues and impact on device performance. The direct tunneling gate current in transistors with alternative gate dielectrics is investigated, and important material parameters such as the tunneling effective masses are extracted. He recently explored the scaling limits of alternative gate dielectrics based on their direct tunneling figures-of-merit and gate leakage requirements for future CMOS technology generations. Guidelines are provided for the selection of gate dielectrics to satisfy the off-state leakage current requirements of future high-performance, low operating power, and low standby power technologies. He has also worked on the integration of two different metal gates in a CMOS process in an attempt to eliminate the problems of poly-silicon gate depletion, high gate resistance, and dopant penetration. This work resulted in the first demonstration of a dual-metal gate CMOS technology using titanium and molybdenum gate electrodes. He also employed the interface dipole theory to explain the experimental observation that metal workfunctions on high-k dielectrics differ appreciably from their values on SiO2 or in vacuum, and provided additional guidelines on the choice of gate materials for future CMOS technology incorporating high-k gate dielectrics.
He has authored or co-authored more than 30 journal and conference papers, and has written a book chapter on MOS transistor gate oxide reliability with Professor Chenming Hu.
Sergei
Kucheyev is a student in the Department of Electronics
Engineering at the Australian National University in Canberra
and his supervisor is Professor Chennupati Jagadish. Sergei Kucheyev’s
research has focused mainly on ion-beam processing of group-III-nitride
and ZnO semiconductor devices. Ion-beam-produced defects can severely
alter all material properties. Hence, an understanding of ion-irradiation-produced
defects is essential if potential applications of ion implantation
for the fabrication of III-nitride- and ZnO-based electronic devices
are to be fully exploited. Emphasis of Sergei’s project has been
on an understanding of (i) the evolution of defect structures
in III-nitrides and ZnO during ion irradiation and (ii) the influence
of ion irradiation on structural, mechanical, optical, and electrical
properties of these materials. In addition to ion-beam processes,
Sergei’s current research interests include the deformation behavior
of brittle semiconductors (in particular, GaN and ZnO) and basic
properties of defects in wide band gap semiconductors.
His project has resulted in the identification of a range of new and technologically important phenomena in group-III-nitrides and ZnO during ion implantation. These phenomena include (i) an unexpected and rather complex behavior of damage accumulation during ion irradiation, (ii) ion-beam-induced phase transformations in III-nitrides, (iii) local stoichiometric imbalance and associated material decomposition during ion implantation as well as during post-implantation thermal annealing, (iv) an intriguing microstructure of defects in ion-irradiated III-nitrides and ZnO, and (v) the evolution of implantation-produced defects during thermal annealing. An understanding of these phenomena is important for a successful application of ion implantation in the fabrication of electronic devices. Sergei’s research on mechanical properties has led to a significantly improved understanding of the plastic deformation behavior of GaN and ZnO, which is crucial for the estimation and control of contact-induced damage in GaN- and ZnO-based electronic devices. During his Ph.D. work, Sergei has published more than thirty papers in prime journals in the field.
He has recently been awarded a highly prestigious postdoctoral fellowship at Lawrence Livermore National Laboratory (LLNL) in the U.S.A. Only up to two Fellowships in all fields of research are awarded each year with typically several hundred applicants from all over the world for the three-year program. Sergei is planning to start his appointment as a Distinguished Lawrence Fellow at LLNL in the latter part of 2002.
T.
K. Ghosh is a student in the Engineering Department at
Lancaster University, Lancaster, UK and his supervisor is Professor
R. G. Carter.
T. K. Ghosh’s research interest is on 3-D simulation and design optimisation of multistage depressed collectors for high efficiency travelling wave tubes. Travelling wave tube (TWT) is a linear beam microwave device and it is an important part of any satellite and air-borne communication system. Multistage depressed collector (MDC) is one of its major components; other two are electron gun and slow-wave structure. A dc beam, generated from the electron gun, transfers some its energy to the input rf wave through a complex process and the rf gets amplified during its travel through the length of the slow-wave structure which is then taken out from the interaction region. The purpose of a collector is to recover most of the remaining power from the spent beam and thereby increase the collector and the overall efficiency. A well-designed multistage collector sorts electrons in the spent beam according to their energy and allow them landing softly which otherwise hit the electrode surface with sufficient energy to generate heat and knock out secondary electrons. Secondary electrons play the detrimental role in collector efficiency if they are collected at a lower depressed electrode from where they were generated. They introduce noise to the amplified signal if stream back towards the interaction region, which is highly undesirable. Experimental results have shown that graphite and carbon, which have low secondary electron emission properties, can be used as electrode materials to suppress the secondary electron emission successfully to a significant level. Use of asymmetric collector geometries and the application of magnetic field in the collector region have proved to be effective in recapturing the secondaries. A fully 3-D simulator LKOBRA (MF) – mainframe version of Lancaster KOBRA has been developed at Lancaster University, UK, which is capable of simulating the multistage collectors including the effects of secondaries and the magnetic field. It is based on KOBRA3# (originally developed for the simulation of ion sources) that has been modified and the pre- and post-processors of the package have been included.
Efficiency is a prime concern in space applications; TWT is no exception. It is always desirable to optimise the collector performance to maximise the overall amplifier efficiency. At first the potentials at different electrodes are optimised to achieve maximum possible theoretical efficiency. The number of collector stages is restricted due to the compromise among efficiency, weight and complexity in fabrication and power supply. A computer code based on the well-known hill climbing technique has been developed where all possible combinations of the electrode potentials are considered in such a way that the area under the spent beam curve covered by the electrodes is maximum for maximum power recovery. This makes the algorithm robust and reliable. It is also simple to implement. In the next step the geometry of the collector electrodes is optimised using an automated design package that is based on the 3-D simulator LKOBRA (MF). This package has been developed using a genetic algorithm. A genetic algorithm creates a new geometry through a search procedure that works from a population simultaneously. New set of geometries is generated using three basic operators, namely reproduction, crossover and mutation. The efficiency is used as the fitness parameter in the genetic algorithm that produces a new population of geometries. It acts as the deciding parameter for the changes in the collector geometry to be made. This package has been used to optimise the efficiency of a 4-stage symmetric collector to about 90% and for a 3-stage asymmetric collector to nearly 84%. In both cases the effect of secondary electron emission has not been considered which will be included in the future work.
As our current winners finish their Fellowship terms, we wish them success in their research and future endeavors. The competition for 2002 EDS Fellowship Awards is ongoing; the winners will be announced in July 2002.
Ilesanmi Adesida
EDS Educational Activities Chair
University of Illinios
Urbana, IL, USA