Renuka P. Jindal
Renuka P. Jindal |
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Each year, the IEEE Electron Devices Society confers the Paul Rappaport Award to the best paper published in an EDS publication. The recipient(s) is awarded a certificate and a check for $2,500, presented at the International Electron Devices Meeting (IEDM).
The winner of the 2000 award is a paper entitled, "Silicon-on-Nothing (SON)–An Innovative Process for Advanced CMOS," which appeared in the November 2000 issue of Transactions on Electron Devices, and was authored by Didier Dutartre, Malgorzata Jurczak, Damien Lenoble, Jose Martins, Stephane Monfray, Roland Pantel, M. Paoli, Jorge Luis Regolini, Pascal Ribot, Thomas Skotnicki, and Beatrice Tormen, and has been selected as the best paper in an EDS publication during 2000. The 2000 award will be presented at the IEDM on 3 December 2001 in Washington, D.C. The following are brief biographies of the eleven winners.
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Didier Dutartre, born in 1956, received the engineering degree in Material Physics from the Institut des Sciences Appliquées de Lyon, France, in 1979, and the Ph.D. degree in 1983. His doctoral research dealt with thermodynamics and liquid phase epitaxy of III-V compounds. He then joined the Centre National d'Etudes des Télécommunications (CNET) as researcher in Material Science. From 1983 to 1989, he developed the lamp zone melting recrystallization technique for the fabrication of thin silicon-on-insulator films. Between 1989 and 1994, he worked in reduced pressure rapid thermal CVD and started the CNET research activities on SiGe epitaxy. In 1994, he joined the Centre Commun Crolles, a consortium between CNET and STMicroelectronics, where he developed high temperature Si epitaxy, in situ doped Si poly processes, and low temperature Si/SiGe epitaxy. In 1999, he joined STMicrolectronics where he is presently leading R&D activities in epitaxy and poly. He holds more than 20 patents and has about 100 publications in these fields. He is married and has two children.
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Malgorzata Jurczak received M.Sc. and Ph.D. degrees in electrical engineering from the Warsaw University of Technology (WUT), Poland, in 1991 and 1997. In 1991, she joined WUT where she worked on modeling of MOS SOI devices. In 1994, she was with NMRC, Cork, Ireland, and in 1997 with Kyung Hee University, Seoul, Korea. In 1998, she joined CNET Grenoble, France, Telecom. She was involved in development of 0.18 and 0.12-µm CMOS process and alternative approaches for sub-0.1 µm CMOS. In 2000, she joined IMEC, Leuven, Belgium, where she is in charge of 100-nm CMOS technologies development. She holds 15 patents and authored 40 papers. She received the Best Paper Award at ESSDERC 2000.
Damien Lenoble received the Engineer Diploma, the M.Sc. Degree in electrical engineering (1996) and the Ph.D. in Semiconductor Physics and Technology (2000) from the National Institute of Applied Science of Toulouse. His Ph.D. work was performed in the France Telecom R&D Center of Grenoble. His studies were focused on the investigation of ultra-shallow p+/n junctions and their impact in deep sub-micron CMOS technologies. He particularly worked on alternative doping technique such as plasma doping. Since 2000, Damien Lenoble has joined ST Microelectronics (Crolles-France) where he is leading the ion implantation R&D with a particular involvement in the development of advanced technologies. (No photo was available.)
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Jose Martins was born in Saint-Jean de Maurienne, France, in 1971.He received the B.Tech. Degree in industrial computing science in 1991 from Cluses university. In 1993, he joined STMicroelectronics, Crolles, where he worked in metallic deposition (PVD). In 1996, he joined the Centre Commun Crolles, a consortium between CNET and STMicroelectronics, where he developed the new architectures for advanced MOS devices (SON, notched gate). His work was dedicated to developing an isotropic plasma process in order to etch selectively the tunnel in SiGe. He is currently working in thermal treatment for 300-mm equipment valuation.
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Stephane Monfray was born in Lyon, France, in 1975. He received the Engineer degree in physics and the postgraduate Diploma in microelectronics in 1999 from the Institut National des Sciences AppliquŽes (INSA), Lyon, France. In 1998, he was with the Laboratoire d'Electronique, de technologie et d'instrumentation (LETI) where he was involved in electron beam lithography, and in 1999, he was working with the LETI and INSA on silicon nanostructures. He is currently pursuing the Ph.D. degree with France Telecom R&D, Meylan, France, and STMicroelectronics, Crolles, France. His work is dedicated to the development and characterization of new architectures for advanced MOS devices, and particularly the silicon-on-nothing (SON) project.
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Roland Pantel was born in Pont de Montvert, France in 1949. He graduated as a Physics Engineer from INSA Lyon in 1974 and received his Ph.D. on plasma surface interaction from University of Orleans in 1977. From 1977 to 1980, he worked as a research assistant at the Plasma Laboratory of the Physics Department of University of Montreal, Quebec, Canada. From1980 to 1999, he has been at CNET France Telecom, Meylan, France, as a Research Engineer where he developed physical and chemical characterization techniques using Auger electron spectroscopy, focused ion beam, energy filtered transmission electron microscopy, and electron energy loss spectroscopy. In January 2000, he joined STMicroelectronics Crolles were he is now in charge of transmission electron microscopy and spectroscopy analysis research and development.
M. Paoli, photo and bio not available.
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Jorge Luis Regolini received his M.Sc. from Centro Atomico Bariloche (Argentina) and graduated from Strasbourg University (France) with a thesis in Solid State Physics. He was then with the Atomic Energy Commission in Argentina as a researcher on Semiconductor Physics and Technology. At the EE Dept. (Stanford University, USA) he worked as a post-doctoral fellow in laser processing for silicon recrystallization and silicide formation. Since 1986, he is with France Telecom CNET-CNS involved on RT/RPCVD for the selective deposition of epitaxial Si/SiGe and silicides. He has presented several invited papers in that field, concerning mainly material fabrication and characterization, kinetics, and kinematics aspects of reduced pressure single wafer reactors. He is also working in silicide deposition by CVD for contacts and interconnects. Since 1999, he is with STMicroelectronics (Crolles-France) as Technical Staff Engineer on Advanced Dielectrics for new generations of DRAMs and gate stacks. He holds several patents and more than 100 publications in these fields.
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Pascal Ribot was born in Ales, France, in 1970. He received the Diplôme d'Etudes Approfondies de Microélectronique in 1996 at the Université de Grenoble. He joined first the Centre National d'Etudes des Télécommunications-Grenoble in 1998, and then ST Microelectronics Central R&D, Crolles, France in 1999, where he obtained the Ph.D. degree. His research interests included non-selective and selective epitaxy by RTCVD of silicon and SiGe layers for bipolar and advanced CMOS applications. He is presently working in the CVD Process Engineering group at Crolles.
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Thomas Skotnicki received the Engineer and the M.Sc. degrees in Electronics from the Warsaw University of Technology, Warsaw, Poland, in 1979, and the Ph.D. degree (with honors) also in Electronics from the ITE CEMI, Warsaw, in 1985. In 1986, he joined the France Telecom R&D (CNET), Grenoble, where he first worked on CMOS modeling and next managed test and development of MOS devices. In 1992, he received from the INPG the French Diploma Habilité à Diriger des Recherches. In 1999, he joined STMicroelectronics Crolles, France, where he manages the Advanced Devices Program running projects on 0.07–0.05-mm FE device and memory modules. He has responsibilities in numerous European projects. He holds 30 patents, has authored several invited papers, over 100 specific papers, a few book-chapters, and has served in Program Committees for IEDM and ESSDERC. From 1993 to 1996, he lectured as a Professeur Vacataire at the INPG, Grenoble. He is a co-recipient of the ESSDERC 2000 Best Paper Award. He is a member of IEEE. In 1998, he was elected a Senior Member of the SEE (French) for outstanding achievements in the field of electricity and electronics.
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Béatrice Tormen was born in Grenoble, France, in 1961. From 1979 to 1996, she worked in different sites of STMicroelectronics in Grenoble as Operator and Trainer both in photo and etching areas. In 1996, she was in Centre National d'Etudes des Telecommunications (CNET Meylan) where she joined the consortium established between CNET and STMicroelectronics as technician in Central R&D. She was in charge of etching processes developments for 0.15-µm then 0.12-µm CMOS (vertical transistor, dielectric pockets, poly SiGe gates, notched gates) and particularly for SON project. She also has been extensively involved in several European projects such as NOVA, ACE, and MEDEA. Now she is involved in evaluation of 300-mm equipment for 0.12- and 0.1-µm technologies.
Renuka P. Jindal
EDS Publications Chair
Agere Systems
Murray Hill, NJ