The role of photonic circuits in fast-reconfigurable interconnects is investigated in terms of capacity and connectivity. Wavelength multiplexed data is processed in parallel in the same photonic components to remove the direct link between power consumption, latency and capacity. Test-bed studies are assessed and the performance of multi-wavelength fast-reconfigurable integrated photonic circuits are discussed with a view to Terabit/second processing in monolithic circuits.

Introduction
The efficient use of increasingly high capacity data networks calls for a higher degree of physical layer reconfigurability. This is especially evident in the high performance computing environment where the processing capability is increasingly impaired by the interconnection networks. A particular challenge is the ability to reallocate bandwidth on the nanosecond-time-scales required for data-packets without incurring undue network latency and unacceptable power requirements.
High-capacity point-to-point data transmission has been facilitated through broadband fiber-optics and the development of high performance commodity transceiver technologies. Increases in link capacity are set to continue through the standardization of 100 Gb/s Ethernet and emerging high-line-rate, wavelength-agile transmitter modules. Photonic circuit integration is enabling the deployment of ultra-low-power parallel transceivers for low-power parallel optical interconnects [1] and providing a route to compact, high-capacity wavelength-multiplexed transceivers [2]. This massive transmitted bandwidth will however further exacerbate electronic switch and router design with packet-time-scale routing still requiring multiple electro-optic conversions, buffering, signal processing and regeneration.
Switching data at the photonic layer offers considerable conceptual advantages. The routing of high-capacity data may be controlled with a low-speed electronic control plane, avoiding complex, parallel, broadband electronic circuitry. Wavelength channels may be routed, split and combined in parallel without the intrinsic need for electrical power. Data can be transferred between wavelength channels without incurring delay and with low optical power penalty. However, power consumption in space and wavelength switches can be high. Customized photonic circuits and sophisticated specialized components can lead to complex physical layers requiring a high control overhead, complex packaging and large physical footprint. The scaling in terms of both connectivity and capacity remains unclear. Photonic integration is commonly cited as a route to addressing these short-comings. The reduced coupling losses, lower numbers of cooler circuits, the co-location of multiple active elements and reduced numbers of fiber pigtails can lead to reductions in power consumption, packaging materials, delays in data transmission and control complexity. Additionally, the parallel processing of multiple wavelength channels may enable further reductions in power and system complexity.
In this paper, studies on the performance of high capacity photonic switches are presented which exploit broadband parallel routing of wavelength multiplexed data and the merits of electronic control. Simulation studies address the scaling of capacity and connectivity alongside comparative test-bed assessment. Ultra-compact photonic integrated circuits are assessed for broadband and low-penalty routing. Routes to higher levels of photonic integration are identified for power-efficient, low-latency interconnection, drawing on advances in state-of-the-art materials technology, active-passive integration, ultra-compact circuit technologies and fiber array alignment techniques.

Figure 1: A high capacity wavelength multiplexed interconnect network

Scaling in Photonic Switches
Wavelength division multiplexing with commodity transceiver technologies allows the opportunity to map high-capacity parallel data busses directly to parallel wavelength channels. By avoiding de/serialization and wavelength level granularity it is possible to maintain time-compressed data packets. These multi-wavelengths data packets may subsequently be routed by means of just one switch, avoiding de/multiplexing within the switching network. One active element operates on multiple wavelength channels to afford order of magnitude space and power consumption savings [3,4]. An interconnection diagram based on a broadcast and select switching network is shown schematically in figure 1. Three WDM transceivers are shown interconnected via the central switching networks.
The switching network in figure 1 is explored as a low-power consumption, low-latency and low-power-penalty switch fabric. The network comprises arrays of semiconductor optical amplifier (SOA) gates for the switch-select function. SOAs enable broadband gain of several Terahertz bandwidth, high off-state extinction for crosstalk suppression, and the feasibility to switch between the on and off states on nanosecond packet time-scales. The input couplers are drawn vertically on the left hand side of the SOA gate arrays, while the outputs are shown in the horizontal plane for clarity. This arrangement allows a doubling in connectivity for each added pair of splitters on the input and output. A switch with N pairs of inputs and outputs therefore requires 2Nlog2N splitters and one active element for each path. Only N powered elements are required at any given time for the full switch circuit. The possible number of connections N is studied for circuits which may be subsequently be used as building blocks in more sophisticated multi-stage interconnection networks. Important physical layer performance metrics such as 1) power penalty, the degradation in receiver performance due to the presence of the switch, and 2) input power dynamic range over which acceptable performance is possible, therefore become critical. The data in Figure 2 quantify power penalty performance in terms of the input powers for the wavelength multiplexed packets.

Fig 2: Power penalty performance of a wavelength multiplexed packet switch.

Power penalty is assessed as a function of the number of wavelength channels and the input power for each wavelength channel. The contours indicate the simulated power penalty. The data points indicate maximum and minimum tolerated input powers as identified in test-bed studies [5]. The number of wavelength channels also impacts the aggregate data rate, and therefore this is specified on the top axis in figure 2. Close agreement between simulation and test-bed data in the observed trends is identified with the low power penalty simulation contours aligning closely with the regimes of low bit error rate performance in the test-bed study. The input optical powers which give lowest power penalty performance are relatively low, and combined with an optical gain exceeding 15 dB in the SOA gate, this enables a high power margin for the multiplexers and power splitters. Indeed a scaling of 8¥8 interconnection is believed to be feasible for 100 Gb/s/path aggregate capacity from the test-bed analysis [5]. Increasing the line rate for each wavelength channel is also a possibility with simulations indicating an optical power penalty of 1.5 dB for 10¥40Gb/s aggregate capacities for the same operating conditions. Further performance enhancement may be anticipated for increased input saturation powers in the SOA gate, which may be feasible either though a reduction in operating gain or further customization of the epitaxial design.

Broadband Integrated Switches
Ultra-compact sub-mm2 integrated switch circuits have been devised at the University of Cambridge specifically for the routing of wavelength multiplexed data packets [3,6]. To reduce the size and facilitate loss-free operation, compact 4 µm wide total-internal-reflecting mirrors have been implemented in combination with SOA gates and tapered-waveguide SOA splitters. Figure 3 shows a schematic layout of one such circuit [6]. The widths of the input and output waveguides are increased as they approach the central splitter network. The partially-reflecting deep-etched mirrors then separate the data packets into two streams. These enter the central SOA gates and are then routed to the required output through appropriate electronic control.
Low optical power penalty operation has been measured without evidence of an error floor for wavelength multiplexed data packets. Dynamic routing studies have demonstrated the error free switching of 8¥10Gb/s microsecond-duration wavelength-multiplexed packets [3]. Drive currents of only 30 mA per active gate have been used, corresponding to less than 50 mW electrical drive power for each 80 Gb/s aggregate capacity path. More recently, the designs have been modified to enable to low-penalty (<0.1 dB) routing at 10 Gb/s line rate in the first monolithically integrated 2¥2 quantum dot switch [6].

Figure 3: Schematic representation of the 2¥2 integrated switch circuit.

Larger Scale Photonic Integration
Higher connectivity monolithic circuits benefit from the integration of the active switching devices with low-loss and penalty-free passive routing components. Active-passive integration technologies have been extensively researched at COBRA to create monolithic circuits with application in wavelength multiplexed data routing. Multi-stage epitaxial growth is implemented for the integration of active circuit elements such as amplifiers, lasers, modulators and detectors, with passive waveguide components such as ultra-compact arrayed waveguide grating (AWG) wavelength multiplexers and compact low-loss, low-reflectivity splitters. New advanced materials are also being developed to improve the intrinsic device properties. Important breakthroughs have been made in the development of polarization insensitive quantum dot amplifiers and laser devices in the important low-loss 1.5 µm window for Silica fiber [7]. Such developments are anticipated to further relax the operating regimes for the circuit concepts which have already been prototyped.
The integration of AWGs with switches has allowed the development of 2¥2 switches which space switching with the additional granularity of each wavelength channel. The image in figure 4b shows one such component where up to four wavelengths may be routed independently of one another to realize an integrated packet-time-scale reconfigurable add drop multiplexer. The integration of AWGs with SOAs has also enabled data to be transferred across wavelength channels (wavelength conversion) at line rates of up to 80 Gb/s operation without incurring errors, within a compact circuit area of 1.7¥3.5µm2 [8]. The circuit exploits the optically-induced gain and phase modulation in the SOA with the transfer function of the AWG wavelength filter to remove the slow distortion components from the output channel, thus enhancing the operating bandwidth of the complete circuit. This four channel device is in principle also able to convert multiple wavelength channels simultaneously.
The further miniaturization of circuit elements has addressed wavelength filter design. AWGs have been reduced to sub-millimeter proportions using a double etch process [9]. This enables both deep etched curved waveguides with extremely low bend radii for a compact device, and shallow etch access waveguides for reduced losses. The increased scattering losses from the deeply etched guides are compensated by the reduced device dimensions. A 4¥4 demultiplexer with a 400 GHz channel spacing has been made with bending radii of down to 30µm to create a device size of 230¥300µm2 as shown in figure 4c. An insertion loss of less than 5 dB is measured. Such compact geometries may facilitate the introduction of wavelength management and noise control to facilitate even lower penalty performance for multi-stage switch fabrics.

Figure 4: A mosaic showing examples of integration technologies being developed for broadband photonic applications at COBRA. a) An atomic force microscope image of a quantum dot active layer, b) An integrated reconfigurable add drop multiplexer circuit, c) A miniaturized AWG, and d) Precision multi-fiber alignment.

Precision Fiber Alignment
The attachment of fiber pig-tailing to multiple input and output waveguides of a photonic switch is a particularly challenging aspect in the packaging of integrated circuits with implications for circuit layout and deployment. Innovative procedures are being investigated for the fine positioning of fiber arrays for multi-port photonic integrated circuits. Here the metal supports for the fibers are deformed through locally induced heating using laser-welding techniques. Figure 4d shows the example of a four port InP circuit pigtailed to lens ended single mode fibers. The technique enables sub-micron alignment accuracies by eliminating the impact of eccentricities in the lenses and inaccuracies in the supporting v-groove substrates to facilitate coupling losses of down to -3dB [10]. Devices with up to eight inputs and outputs have been pigtailed using this approach.

Summary
Techniques to reduce the power consumption and system level complexity of switching networks are being addressed through the use of multi-wavelength integrated photonic switching circuits. Simulations, in agreement with test-bed studies have identified the possibility of 8¥8 switch interconnection with aggregate data rates of 100Gb/s per path, identifying a route to Terabit/second routing in a single stage switch fabric. Compact sub-millimeter monolithic 2¥2 switches have been prototyped for high-capacity, low-power-consumption and low-penalty operation. More sophisticated scalable integrated circuits are now anticipated through the leveraging of advances in material technology, ultra-compact filter technologies and active passive integration techniques. Future work will explore power-efficiency in higher connectivity integrated switch fabrics and the role for wavelength multiplexed data packet routing in interconnect circuits.

Acknowledgements
The author is supported by a Marie Curie chair at the Technical University of Eindhoven. The network of excellence ePIXnet is acknowledged for supporting a staff exchange program with the University of Cambridge where the author also holds a visiting fellowship. Prof Ian White at Cambridge University and Dr Madeleine Glick at Intel Research are thanked for their inputs. Colleagues at COBRA, Technical University Eindhoven are thanked for their contributions.
References
[1] R. Nagarajan et al., “400 Gbit/s (10 channelx40 Gbit/s) DWDM photonic integrated circuits”, Electronics Letters, 41, 6, 2005
[2] Journal of Lightwave Technology, Special issue on optical interconnects, 22, 9, September 2004
[3] K.A. Williams, G.F. Roberts, T. Lin, R.V. Penty, I.H. White, M. Glick and D. McAuley, “Monolithic 2¥2 optical switch for wavelength multiplexed interconnects”, IEEE Journal of Selected Topics in Quantum Electronics, Special issue on integrated optics and optoelectronics, 11, 78-85, 2005
[4] M. Bachmann, P. Doussikre, J.Y. Emery, R. N’Go, F. Pommereau, L. Goldstein, G. Soulage and A. Jourdan, “Polarisation-insensitive clamped-gain SOA with integrated spot-size convertor and DBR gratings for WDM applications at 1.55 µm wavelength”, Electronics Letters, 32, 2076-2078, 1996
[5] T. Lin, K.A. Williams, R.V. Penty, I.H. White, M. Glick and D. McAuley, “10¥10Gb/s packet routing with single stage SOA switch for multi-port interconnects”, IEEE Photonics Technology Letters, 18, 691-694, 2006
[6] S. Liu, X. Hu, M.G. Thompson, R.L. Sellin, K.A. Williams, R.V. Penty, I.H. White and A.R. Kovsh, “Low penalty monolithic 2 x 2 quantum dot switch”, proceedings ECOC, Post-deadline paper Th4.5.6, 2006
[7] Tangdiongga, E., Y. Liu, J.H. den Besten, M. van Geemert, T. van Dongen, J.J.M. Binsma, H. de Waardt, G.D. Khoe, M.K. Smit and H.J.S. Dorren, “Monolithically integrated 80 Gbit/sec AWG-based all optical wavelength converter”, IEEE Photonics Technology Letters 18, 1627 (2006)
[8] Y. Barbarin, X. J. M. Leijtens, E. A. J. M. Bente, C. M. Louzao, J. R. Kooiman and M. K. Smit, “Extremely small AWG demultiplexer fabricated on InP by using a double-etch process”, IEEE Photonics Technology Letters, 16, 11, 2478-2480, 2004
[9] S. Anantathanasarn, R. Nötzel, P. J. van Veldhoven, F. W. M. van Otten, T. J. Eijkemans, and J. H. Wolter, “Stacking and polarization control of wavelength-tunable (1.55 µm region) InAs/InGaAsP/InP (100) quantum dots”, Applied Physics Letters, 88, 063105, 2006
[10] J.H.C. van Zantvoort, S.G.L. Plukker, E.C.A. Dekkers, G.D. Khoe, A.M.J. Koonen, H. de Waardt, “Laser supported fibre array alignment with individual fibre fine positioning”, proc. ECTC, Florida, 266-271, 2005