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The continuing shrinkage
in the “rad-hard” foundry market is making it more difficult
to secure qualified parts that meet the power, performance, and
low cost demands of the modern radiation-hardened system. Today’s
relatively small market for rad-hard components makes it difficult
for the few remaining suppliers of these parts to offer state-of-the-art
products (e.g., G4 microprocessors or high speed and density memory)
to the manufacturers of satellites and other space systems. This
has prompted the designers of these systems to adopt a variety of
strategies to ensure the viability of their electronics in the harsh
radiation environment of space while simultaneously controlling
costs. These strategies range from up-screening commercial parts
to the radiation-hardening-by-design (RHBD) approach.
In RHBD, electronic components are manufactured to meet specified
radiation performance criteria, but the techniques employed to meet
these criteria are implemented either in layout or in the application
architecture and not in the fabrication process. RHBD is typically
considered distinct from radiation-hardening-by-process (RHBP).
Radiation hardening via process modifications is the traditional
approach used by rad-hard foundries (although it should be noted
that these foundries typically implement both RHBP and RHBD techniques).
While RHBP has the advantage of being an extremely reliable means
of achieving hardened components, RHBP is susceptible to low volume
concerns such as yield, process instability, and high manufacturing
costs. These drawbacks, when coupled with the post Cold War contraction
of the government electronics market, caused a dramatic industrial
exodus from rad-hard manufacturing. The number of rad-hard foundries
has gone from more than ten in 1985 to two dedicated foundries today
[1].
In order to leverage the economy-of-scale provided by the commercial
electronics industry, some rad-hard electronics customers are looking
at RHBD as a potentially lower cost solution to persistent radiation
threats. The RHBD approach makes sense in today’s evolving
electronics marketplace where semiconductor fabrication is becoming
more detached from integrated circuit design. IC developers, in
companies both large and small, now submit their ASIC designs to
external foundries for fabrication. The growth of the field programmable
gate array market is another good example of the increasing detachment
between design and fabrication. The RHBD methodology fits this new
model for IC development, i.e., custom circuits are designed for
optimal performance in a targeted radiation environment and fabricated
separately in a high volume commercial technology.
However, it is still an open question whether RHBD alone will ultimately
work. Ideally, the RHBD approach can produce hardened devices on
standard commercial foundry flows, without any modification to the
existing process or violation of design and layout rules. However,
recent R&D efforts have indicated that the discovery of effective,
design rule “clean,” techniques that meet targeted specifications
is a more daunting task than originally thought. Many of the conventional
RHBD techniques such as re-entrant geometries for total ionizing
dose mitigation or dual interlocked storage cells (DICE) for reducing
single event upsets are difficult to implement without corresponding
electrical performance and area penalties of greater than one generation
[2]. Designers for a number of satellite payload manufacturers are
now engaged in activities to identify the design practices that
will minimize the impact of RHBD on their power, speed, and area
targets. Much of this effort relies on detailed understanding of
the available commercial technologies and how these technologies
respond to a specific set of radiation threats. Designers must often
perform detailed modeling and experiments to determine which RHBD
technique needs to be implemented to meet mission requirements.
It is generally believed that the greatest radiation-related threats
to modern electronic components are single event effects caused
by individual energetic particles. Reduced device dimensions and
accompanying technological changes have resulted in increased sensitivity
to single event strikes. Many of the RHBD techniques available for
SEE mitigation rely on redundant architectures, which can have a
deleterious effect on performance and area.
Prohibitive performance, power, and area penalties are not the only
problems that may impact the ultimate efficacy of RHBD. Indeed,
there are other, perhaps larger, unresolved questions including:
costs to the end-user, part traceability, and security. With respect
to the first question, it is still unknown whether the high costs
of commercial parts qualification will be significantly reduced
with the RHBD approach. Thus, even though manufacturing expenses
may be substantially reduced via RHBD, the need to qualify designs
may in the long run erase any cost benefits to the end user. Another
benefit of RHBP and the use of rad-hard foundries is their dedication
to the rad-hard electronics user. In RHBP, problems associated with
the hardness of a particular process or lot may be traced and corrected
for the customer. The commercial foundry is unlikely to provide
this level of support. Lastly with the rad-hard foundry approach,
the lifetime of a classified IC is fairly easy to track, from design,
to manufacturing in a cleared facility, and to ultimate insertion
into a strategic system. By contrast, the manufacturing cost advantage
of RHBD is exactly what makes it a potentially greater security
risk, i.e., fabricating the classified IC in a low cost commercial
un-cleared foundry.
Today there are several groups actively involved in trying to find
answers to these questions. In 2004, the Defense Advanced Research
Projects Agency (DARPA) initiated a program specifically dedicated
to determining the workability of RHBD. Participants in the program
include the Defense Threat Reduction Agency, the U.S. Air Force,
the Boeing Company, ATK Mission Research, and a team of industrial
and academic partners. These research efforts may ultimately reveal
that the best solution may not be found in selecting one hardening
methodology over another but rather in finding the optimal combination
of RHBD and process hardening [3] coupled with a firm understanding
of the impact of technological advancements on the radiation hardness
of a specific system.
- R. Lacoe, D. Mayer, J. Osborn and S. Brown, “New
Strategies for Radiation Hard Electronics,” 2001 MRQW, December
11, 2001
- R. Lacoe, “CMOS Scaling Design Principles
and Hardening-by-Design Methodologies,” IEEE NSREC Short
Course, 2003.
- N. Nowlin, S. McEndree, D. Butcher, “A Radiation
Hardened High-Precision Resolver-to-Digital Converter (RDC)”,
2004 IEEE Radiation Effects Data Workshop, July 22 2004, pp 96
– 103.
Hugh Barnaby can be reached at the ECE Department,
Arizona State University, 1230 E. Speedway Blvd., PO Box 210140,
Tucson, AZ 85721-0104; Phone: +1 480 727-0289; E-mail: hbarnaby@asu.edu.
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