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Historically,
defense and space applications have been primary drivers of the
study of radiation effects in semiconductors. Several years ago,
with the end of the cold war and the (temporary) change of DARPA
to ARPA, there was some decrease in the level of activity in this
area. More recent developments have revived interest in the subject,
including emphasis on space missions, the need to update technologies
to support world stability, homeland security and technology scaling.
One trend in the radiation-hardened electronics community has been
to attempt to use commercial technologies, either commercial off
the shelf (COTS) or hardened by design (HBD) parts, due to the limited
availability of hardened by process options. Consequently, there
has been a good bit of effort in characterizing COTS parts as well
as characterization of advanced commercial processes for radiation
response, such as the DARPA (note the D is back) Radiation Hardened
by Design Program.
Of particular interest is the increased concern over single event
radiation effects in commercial applications that has been occurring
over the past ~ 1-2 years. For example, for the past couple of years,
Cisco Systems has included application notes with “work arounds”
for single event upsets in their high speed commercial routers.
Terrestrial single event errors have been of concern for some time
in high reliability computers and commercial DRAMs. With advanced
CMOS device dimensions scaling to the sub-100 nm regime, and supply
voltages approaching 1 volt, the tight spacing and low noise margins
are problematic for terrestrial single event errors in commercial
logic and SRAM circuits. In fact the IEEE Nuclear and Space Radiation
Effects Conference (NSREC) this year included a short course by
Dr. Robert Baumann of Texas Instruments on this subject.
The growth of commercial interest in this area provides opportunities
for researchers in the radiation effects community to leverage the
knowledge gained in the work on radiation-hardened applications.
Among the opportunities are:
Study of radiation effects in new materials and advanced device
structures:
Leading edge technology options include the use of silicon-on-insulator,
high-k gate dielectrics, low-k interlevel dielectrics, copper metallization,
and strained silicon. Scaled bulk and SOI CMOS both can exhibit
parasitic bipolar enhancement of radiation-induced photocurrents.
The response of these materials and devices to radiation should
be understood and incorporated into analysis of the circuit responses.
Modeling and simulation of interactions involving multiple devices:
The high packing density of advanced circuits increases the probability
that multiple devices may be affected by a single event, and contribute
to the resulting response. For example, multiple devices in a common
well may be impacted by a single event that collapses the well potential.
Nuclear reactions may produce products that deposit charge at multiple
circuit nodes. These types of multiple device events may be the
weak link in many cases and must be accounted for in design topology.
Understanding and accounting for the complex 3D structures of
today’s circuits (including the overlayer materials):
Below the active devices, complex doping profiles on junctions,
wells, and substrates (which may include the use of SOI) can affect
single event charge collection. At the active device level, nonplanar
devices (such as FinFETs) are proposed to address scaling limitations.
Above the active layer are complex stacks of high-Z metals and interlevel
dielectrics with which ionizing radiation interacts prior to reaching
the devices. Understanding and accounting for how particles interact
with the multiple materials and geometric structures and deposit
energy is vital to predict and understand the circuit response.
Development of advanced simulation technology to reduce testing
requirements:
Commercial applications tend to be very cost sensitive. Radiation-hardened
applications may be required to operate in environments for which
it is not possible to test. In all cases, iteration of technology
or design with repeated testing is very costly and time consuming.
A more comprehensive “virtual testing” capability is needed
to reduce the testing burden. The advent of inexpensive powerful
parallel computing capabilities has opened the door to making this
a feasible option.
Development and application of hardened by design techniques
to address commercial needs:
There has been substantial work in the development of device and
circuit topologies that are optimized to mitigate radiation effects.
In many cases, the tradeoff (increases area, decreases performance)
associated with these techniques may not be acceptable for commercial
applications. However, there may be applications where some of these
techniques may be leveraged in improving the radiation tolerance
of commercial designs.
Incorporation of radiation effects as a reliability design criterion
in commercial design flows:
For the most part, the impact of radiation on circuits is simulated
through a combination of energy deposition, device response, and
circuit level response simulation techniques. The process is not
highly automated, nor are the models and capabilities well integrated
into electronic design automation (EDA) tool flows. The opportunity
exists to integrate radiation effects as reliability considerations
in design flows, such as incorporation of radiation-aware compact
models, design rules, and parasitic extraction into process design
kits.
These are exciting times for the study of radiation effects. Wrestling
with how to meet the continuing needs of strategic and space applications
in a challenging business environment, characterization of commercial
technologies for radiation response, application of radiation-effects
experience to address growing commercial concerns, and development
of radiation-aware design environments present ongoing opportunities
for researchers in the radiation effects community.
Michael Alles can be reached at Vanderbilt University Institute
for Space and Electronic Devices, Box 1608, Station B, Nashville,
TN 37235 USA; Phone: +1 615 343-8829; Fax: +1 615 343-9550; E-mail:
Mike.Alles@vanderbilt.edu.
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