The 2nd IEEE Asia-Pacific Conference on ASIC (AP-ASIC), hosted by the IEEE ED/SSC Seoul Chapter, was held at Hotel Shilla Cheju, Cheju, Korea, 27–30 August 2000. The objective of AP-ASIC is to promote research and development activities of solid-state circuits in the Asia-Pacific region. AP-ASIC 2000 featured 2 tutorials, 3 keynote speeches, 4 embedded tutorials, and 97 presented papers (83 papers in 17 regular sessions and 14 papers in 3 special sessions). The total number of registrants from five countries (Korea, Taiwan, Japan, the United States, and India) was 170 and there were 22 tutorial attendants. The brief summary of the technical activities follows.
Two tutorials on RF ICs and Data Converters were given on 27 August. The tutorial, “Recent developments in CMOS RF integrated circuits,” by Prof. T. Lee of Stanford University emphasized CMOS RF ICs. Scaling trends of CMOS processes, capacitors, passive mixers, broadband noise models, power-constrained LNA design, a new phase noise theory and its implementations, and a circuit example of GPS receiver was explained in detail. The tutorial, “Data converters for communications,” by Prof. B. Song of the University of California, San Diego, detailed (1) high-speed A/D conversion techniques including flash ADCs, folding ADCs, and pipelined ADCs; (2) low-spurious A/D conversion techniques, including high-resolution techniques, digitally calibrated pipeline ADCs, and background calibrated folding ADCs; and (3) low-spurious DACs.
Dr. Y. Huh, Vice President of Hyundai Electronics, outlined four ASIC technologies for the next decade: deep-submicron process technology, design technology, system On A Chip technology, and manufacturing technology. Dr. W. Rhines, President and CEO of Mentor Graphics, emphasized design reuse, system verification, and design performance dominated by interconnection effects. Prof. R. Kohno of Yokohama National University, Japan, presented an overview of R&D, core communication technologies, and requirements of Intelligent Transport Systems (ITS).
Two papers on VGAs for high-frequency and low-noise applications were presented. A 200-MHz VGA achieved controllable gain range from –45 dB to 45 dB. The low-noise VGA for low-frequency applications described the noise optimization method of the VGA. Various A/D converters with current-mode techniques were presented as well as an A/D converter with low-power consumption (8 mW).
CMOS logic circuits for high-speed application were presented with capacitor coupling techniques and high-speed sense amplifiers. Dynamic logic circuits seemed to be the driving force of high-speed CMOS logic design. A session was devoted to digital circuits related to system design (such as image downscalers, processors of parallel genetic algorithm, and heterogeneous system interface architecture design) and its verification techniques (such as BIST and STA).
In the sessions for image sensors and MEMS circuits, a multilevel, multiphase change recycling design for low-power LCD drivers, a new algorithm for contrast control implemented in FPGA, and a quad-tree scan technique to reduce the amount of data transfer in image sensor were proposed.
A feedforward offset cancelation limiting amplifier demonstrated an efficient and integrated offset cancelation scheme. A temperature- and supply-voltage independent VCO circuit using a novel bias circuit was presented. Both papers demonstrated measurement results that agreed well with the prediction. A sigma-delta modulator architecture was proposed to reduce intermodulation and noise of tones near fs/2 into the base band. A Volterra series analysis of cascode amplifiers for high-frequency intermodulation analysis provided good insight for the nonlinear characteristics of cascode amplifiers and the guidelines for the optimization. A thorough comparison of different mixer topologies was given in addition to a novel mixer topology that shows good NF, gain, and linearity. Distinguished results on a 3-V, 10-b, 100 MS/s DAC for cable modem application were presented, with proposed switching sequence and deglitching circuit.
The presented papers included 64 ´ 64-b parallel multipliers, a novel power on/off protection circuit for FeRAM, improved VLIW architectures, an efficient method of building crosstalk library, and noise-free microcontrollers.
The special session for ASIC design companies allowed ASIC design and CAD companies to introduce their new products. Various products and ideas were introduced, including microprocessors, CMOS image sensors, and SOC-related issues, new design methodologies, and new placement/routing techniques.
The special session placed an emphasis on the low-power applications of microprocessors. Several papers related to CalmRISC-32 pro-cessors were presented. They were a cache memory system design; design and implementation of a floating point unit; random vector verification method; 150-ľA/MHz, 2.5-V at 130-MHz operation; testability strategy; and DFT methodology with CalmRISC-32. In addition to the CalmRISC-32 microprocessors, there were papers on translation look-aside buffers (TLBs), embedded 16-b microprocessors, and hardware-reduced multipliers.
AP-ASIC 2000 was a highly successful conference, bringing together the Asia-Pacific solid-state research community. The next conference will be AP-ASIC 2002, to be held in Taiwan and continued biennially. We expect growth of the conference in both quantity and quality in the year 2002.
D. Lee, J. Jou, and K. Sasaki
Technical Program Cochairs