RFIC Symposium, Seattle, Washington, 2–4 June 2002

The RFIC Symposium is a leading international conference dedicated to the advancement of integrated radio frequency circuits and subsystems for RF and communication applications. The RFIC Symposium program starts with tutorials and workshops held on Sunday. The technical program takes place on Monday and Tuesday and includes technical papers, a panel session, and a number of invited and special sessions related to the latest advancements in RFIC.

The technical program starts off on Monday morning with a keynote plenary session. The first keynote talk, "Challenges for the next generation of RF integration," will be presented by Behrooz Abdi of Motorola Inc. Mr. Abdi is the vice president and general manager of the Radio Products Division within the Semiconductor Products Sector responsible for RF & mixed-signal ICs and modules for wireless applications. The second keynote talk, "RF design, a historical perspective," will be given by Dr. Ulrich Rohde. Dr. Rohde is president of Communications Consulting Corporation and executive vice president of Strategic Planning at Ansoft Corporation.

A panel session on "RF-CMOS in cell phones: fact or fiction" is scheduled Monday, 3 June, 12:00–1:15 PM. The panelists, representing various industries and academia will discuss their views on the future of high-performance RF-CMOS for mobile handsets. The panel organizers, Natalino Camilleri and Fazal Ali, comment "RF-CMOS development has come a long way towards being implemented in several systems for multiple applications. One can find RF-CMOS in some cordless devices, WLAN and Bluetooth products. However, in cellular handset systems, RF-CMOS has had a difficult time competing with the SiGe BiCMOS technology in offering the "best in class" RF performance while maintaining the lowest power consumption."

The RFIC social reception will be held on Sunday evening and the Microwave Journal/MTT-S reception on Monday evening. The Interactive Forum will meet Tuesday, 4 June,1:20–5:00 PM.

Session Descriptions

Monday, 3 June, 10:10–11:50 AM

Cellular Transceivers

This session focuses on state-of-the-art 2G and 3G transmit and receive IC design techniques. Highly integrated direct-conversion receivers for GSM and WCDMA are discussed in detail. High dynamic range, high-precision, high-efficiency CDMA transmit circuits are also presented.

Efficiency Enhancement Techniques for Handset Applications

This session covers different techniques for improving power amplifier efficiency. Enhancement techniques include variable bias, variable load impedance, envelope tracking/following, and digital pre-distortion. Detailed design, analysis, and results of high-performance Class E amplifiers are addressed.

Integrated VCO

This session presents the latest advances in integrated voltage-controlled oscillators. Various design techniques for improving VCO performances including phase noise, frequency tuning range, and power consumption are reported. The quadrature generation of VCO for direct-conversion transceivers is discussed in three papers.

Optical System ICs

The session opens with an invited paper from Intel that walks the audience through the ins and outs of circuit design for optical systems. It focuses on 10-Gb/s applications as well as on the challenges that the next generation 40-Gb/s optical systems will face. The next paper highlights the design of one of the indispensable components for high-speed systems: a 37–50-GHz VCO for 40-Gb/s applications. The next two papers discuss the design of other components for 10-Gb/s optical systems: first, a 12-channel amplifier array with low cross-talk is demonstrated; then, a low-cost front-end chipset is described and implemented in Si CMOS technology. The session concludes with a presentation on co-simulation of layout and circuit design in order to shorten the design cycle.

Wireless Data System ICs

This session covers a wide range of applications and highly integrated transceivers. An invited paper on 802.11b WLAN technology contrasts a 0.25-µm full CMOS solution with a 0.5-µm SiGe design. Additional papers demonstrate state-of-the-art techniques for Bluetooth, GPS, cordless, and broadband cable modem systems.

Monday, 3 June, 1:20–3:00 PM

LNAs, Mixers and Switches

The papers in this session focus on new developments in key RFIC building blocks for modern cellular systems and span SiGe BiCMOS, BiCMOS, and GaAs technologies. Advances in automatic RF circuit synthesis, high-performance CDMA receiver front-end design, direct conversion WCDMA front-end design, dual-band variable gain mixers, and low-voltage high-power GSM switch design are presented.

High-Frequency Receiver and Converter Technology

This session addresses signal-conversion ICs operating from 2 through 33 GHz using pHEMT and SiGe HBT technologies. The first paper presents a 2–18-GHz high-dynamic range receiver IC utilizing a commercial GaAs pHEMT process. The second paper addresses a 3–33-GHz mixer using distributed topology implemented in pHEMT technology. A Ka-band direct digital receiver IC is reviewed in the third paper. A highly integrated 24-GHz reciever IC utilizing SiGe HBT technology is discussed in the final paper.

PLL and Frequency Synthesizer

This session covers the design techniques for high-speed phase-locked loops in radio frequency synthesizers. Design considerations such as power consumption, jitter, dual band, and high-frequency time delay are reported.

Monday, 3 June, 3:30–5:10 PM

3G Cellular Systems and Chipsets

This session covers both system-level issues and chipsets for 3G CDMA and WCDMA. Multifunction system architectures, digital and RF integration issues, and optimized chipsets are presented. The session concludes with a discussion on 4G technology and architecture challenges.

Low-Noise Amplifiers

Recent advances in fixed- and variable-gain LNAs are discussed in this session. Highlights include a 1-V 8-GHz CMOS variable-gain LNA, 2- and 5-GHz LNAs with gain steps, as well as SiGe BiCMOS and CMOS 5–6 GHz LNAs for WLAN.

Very High Speed Si and SiGe Divider ICs

This session presents divider ICs operating from 14 through 36 GHz implemented in Si and SiGe technology. The first paper reviews a dual-modulus 14.5-GHz divider utilizing Si technology. Next, a 19-GHz static divider in CMOS is presented. A low-power 20-GHz static divider is reviewed, which has been implemented in Si. Finally, a SiGe implementation of a dual-modulus prescaler operating at 36 GHz is discussed.

Power Amplifiers for Handset Applications

This session shows the latest power-amplifier performance for GSM/EDGE and WCDMA applications. Many performances were improved through better bias networks and/or active pre-distortion. Also, an improved CMOS integrated distributed amplifier is addressed.

Tuesday, 4 June, 10:10–11:50 AM

Radio Frequency Integrated Circuits for 3G

This session deals with RFIC and system aspects for third-generation mobile terminals and base stations. Two invited papers demonstrate the first implementations of an integrated even-harmonic-type direct-conversion receiver and of a zero-IF receiver chip for wideband CDMA. Furthermore, a CMOS transceiver chipset and system analysis of base station power amplifiers are presented.

MMIC Technology

The papers in this session address Si, GaAs, and InP MMIC technologies, which enable innovative wireless and microwave applications. New advances in process development of silicon technologies are enabling reduced electromagnetic coupling effects in RFCMOS, the integration of SCR-based ESD protection circuits into RFCMOS, and the novel integration of a short-channel LDMOS technology that is BiCMOS compatible. These developments point to the potential in low-cost RFICs using standard Si processes. In the area of III-V devices, new developments allow the integration of analog and digital functions in an E/D pHEMT process and the demonstration of an InP HEMT-based VCO with heterojunction interband tunnel diode. Finally, a Ka-band MMIC LNA/PA chipset is reported as packaged in a low-cost SMT-compatible technology.

Tuesday, 4 June, 1:20–3:00 PM

Silicon Substrate and Inductor Modeling

Continued advances in developing Si RFIC components require careful consideration of losses in passive components and losses associated with the Si substrate. This session focuses on developments in modeling inductors fabricated on Si substrates. In addition, the influence of conductive substrates on active device behavior is discussed.

SiGe RFIC Process Technologies

RFIC applications now address wireless data as well as mobile communications and broadband tuner applications. The SiGe process is ideal for meeting the needs of these high-frequency applications and is the focus of this session. Several leading companies present their process technologies with respect to RF performance of both passive and active components.

Tuesday, 4 June, 1:20–3:00 PM

Active Device Modeling and Characterization

Development of RFIC components requires precise modeling of active device behavior, including large signal, small signal, and noise effects. This session focuses on developments in the active device modeling occuring in these areas.

RFIC Power Amplifier Technologies

This session focuses on power amplifier technologies and often overlooked RFIC issues such as packaging and passive components. An overview of power amplifier technologies is presented and relevant results in both SiGe and GaAs technologies are discussed.