2002 Symposium on VLSI Circuits

The Symposium on VLSI Circuits will meet 13 – 15 June 2002 in the Hilton Hawaiian Village, Honolulu, Hawaii. This year the technical program committee reviewed 225 submissions to the conference and chose 84 papers for inclusion in the technical program. The unusually high number of submitted top-quality technical papers has resulted in a technical conference that promises to be bigger and better than ever. With these featured papers, it can be truly said that anyone not in Hawaii during the second week of June will miss an unprecedented unveiling of technical knowledge. Papers describing new and innovative demonstrations of leading-edge concepts dominate every session. The three days of technical presentations and the informal evening rump sessions are a companion conference to the Symposium on VLSI Technology, which precedes it at the same hotel. The one-day overlap in the schedules for the Technology and Circuits meetings features a Short Course as well as a joint rump session on the major technical questions being discussed at leading semiconductor companies around the globe.

The scope of the Circuits Symposium covers all aspects of VLSI circuits, such as:

• Circuits for digital, analog, memory, communications, and signal-processing applications, including A/D and D/A
• Processing applications, including A/D and D/A converters, mixed analog/digital functions, and interface circuits
• Systems and architectures related to VLSI circuits
• Fundamentals related to the above subjects, including innovative circuits and device structures
• New System-On-A-Chip circuit applications such as MEMS

The emphasis is on circuit design. Papers are chosen on the basis of originality and quality. Although the circuits need not be implemented in a semiconductor chip, measured results, particularly for analog submissions, are key selection criteria. There will be four invited papers on emerging VLSI circuit technologies: on-chip interconnect, ultra-low-power LSI for mobile communications, biomedical implantable technology, and digital still camera technology.

Technical Highlights

This year we have assembled an array of interesting papers in areas that are at the forefront of integrated circuit design. Among the highlights of this conference are a 1-Megabit MRAM, which is the largest MRAM demonstrated to date, and a 3-GHz Pentium¨ 4 processor, which will feature the unprecedented scaling of a design from 1 GHz to 3 GHz.

Also featured in this conference are two different papers discussing, for the first time, their implementations of DDR II. Data rates as high as 1 Gb/s/pin are detailed in these flagship DRAM memory papers. In the area of ultra low power, one paper describes SOI circuit technology for batteryless mobile systems. A 0.5-V CPU is fabricated using a fully depleted SOI process. Another key innovation explores the novel concept of logic in memory by a ferroelectric functional pass gate. Active device counts are reduced significantly using ferroelectric technology to merge storage and switching functions. In the analog area a 17-mW transmitter and frequency synthesizer for 900-MHz GSM is reported. This work comprehends the importance of the transmitter in a cellular handset since it is often the overlooked component in considering the power dissipation of the overall system.

Invited Speakers

Invited papers are always a high point of the Symposium and focus on both technical information and business implications of technology change by leaders in their fields. At this year's plenary presentations Jim Meindl from Georgia Tech describes his work involving on-chip interconnects. Takakuni Douseki of NTT gives his vision of ultra-low-power LSI design for future mobile communication. Next, Professor Ken Wise of the University of Michigan reports on the progress in the field of biomedical implantable devices. Finally, Hiroshi Tamayama of Fuji Photo Film discusses digital still camera technology.

Rump Sessions

Evening rump sessions are organized around a controversial topic, and experts are recruited to present their divergent views. All aspects of the issue are explored, and a spirited discussion ensues; active audience participation is encouraged! This year the rump session topics for the Circuit Symposium are:

"Scaling limit in a power-limited environment— architecture versus circuit design," "Will high-performance analog survive in deep sub-micron CMOS?" and "Revolution or evolution for memory technology?"

A closer look at the rump session on "Scaling limit in a power-limited environment" gives a good idea of the opportunity provided for candid discussion in topics of interest to experts in this area. Today, power dissipation, both in the active and standby modes is becoming a key issue for desktop computers and mobile communication devices. This panel, organized by Ken Yang of UCLA and Tadahiro Kuroda of Keio University, features an array of panelists who are recognized experts in their particular field.

Scaling Limit in a Power Limited Environment

Panelists:

• Kerry Bernstein, IBM
• Uming Ko, TI
• Alireza Kaviani, Xilinx
• Chenming Hu, TSMC
• Kiyoo Ito, Hitachi
• Masayuki Mizuno, NE

Overlap Day

Another special feature of these Symposia is the one-day overlap in the schedules for the Technology and Circuits meetings. This is an excellent opportunity to meet with members of the opposite discipline to share experiences, frustrations, and ideas for future improvements. In addition to these chance meetings, there is also a joint rump session organized by members of both the Circuits and Technology committees. This year's topic is "SOC (System On A Chip) versus SIP (System In A Package)."

VLSI Circuits Short Course

Stephen Kosonocky of IBM and Koichiro Ishibashi of STARC have organized an excellent one-day Short Course on Wednesday, 12 June 2002. The topic is "Circuit and technology options for controlling leakage." The agenda includes talks by noted experts representing the entire spectrum of the industry:

• Introduction— Stephen Kosonocky, IBM T.J. Watson Research
• Device scaling, leakage components, joint technology and system optimization— David Frank, IBM T.J. Watson Research Center
• Overview of gate leakage and prospects of a technology solution— Toriumi, Tokyo University
• Optimization and control of VDD and Vth— Tadahiro Kuroda, Keio University
• Multi-Vt fully-depleted CMOS/SOI circuits for low-voltage design— J. Kouji, NTT
• Leakage-sensitive logic and circuits— Kaushik Roy, Purdue University
• Low standby power SRAM— Jae-Hoon Jang, Samsun
• Conclusion— Koichiro Ishibashi, STARC

This Short Course is an intense one-day course intended to give attendees an excellent overview of the topic as well as to provide the latest developments in the area. This represents a rare opportunity to hear presentations describing work in a timely technical area by recognized leading researchers teaching others to do what they do best.

Further Information

For registration and other information, visit the VLSI Symposia home page at: www.vlsisymposium.org. Or contact the Secretariats: USA Secretariat, vlsi2002@aol.com, Japan Secretariat, vlsisymp@bacasj.or.jp