Highlights of DAC at ISSCC
year, ISSCC introduced Sunday evening sessions in which experts were
invited to present the state of the art in topics of special interest.
This year, one of these Sunday evening sessions featured papers from
the 39th Design Automation Conference (DAC) that was held in June 2002.
Papers were selected based on their technical excellence as well as
their relevance and interest to ISSCC attendees. The goal was to give
attendees a look at some of the latest developments in design tools
and methodologies. A similar special session of ISSCC papers will be
held June 2003 at DAC, in which DAC attendees will have the chance to
hear selected papers from this year's ISSCC.
This year's session featured four papers that covered design topics
ranging from tool-busting System-On-a-Chip (SOC) design methodologies
to new performance models that one day might support true analog circuit
synthesis. In the first presentation, Aurangzeb Khan of Cadence Design
Systems described the challenges in achieving first silicon success
when building large, complex SOCs under the pressure of reduced time
to market and shorter product life cycles. He drew on the experience
of a number of real-world designs including a 280M transistor graphics
synthesizer and an OC-768 framer-mapper. Khan claimed that pushing the
design envelope requires us to break down the barriers that exist today
between front-end designers, back-end designers and CAD tool developers.
Bringing these individuals into a single design team allows the development
of custom design flows that significantly extends the capabilities of
commercial design tools. For example, resynthesizing modules after floorplanning
and placement allows for more effective clock distribution and noise
management. In another example, Khan showed how diagonal routing was
used to achieve a 20% reduction in path delay and a 10% reduction in
the area of a high-performance RISC core.
In the second presentation, Achim Nohl of Aachen University of Technology
(Germany) described a new technique for speeding up instruction-level
simulation of embedded processors. Most commercial tools rely on interpretive
simulation in which the code to be simulated is fed into a program that
mimics the instruction decoding and execution of the hardware processor.
Recently, there has been considerable interest in compiled simulation
in which instruction decoding occurs at compile time. This significantly
speeds up simulation at the expense of flexibility, since it is no longer
possible to model run-time changes to the code, such as program loads
or self-modifying code. Nohl described a new technique that he calls
"Just in Time Cache Compiled Simulation" (JIT-CCS). Instructions
are decoded at run time, so full flexibility is maintained. Once decoded,
however, an instruction's decoded function is stored in a run-time cache.
The next time that instruction is executed, decoding can be bypassed
and the instruction can execute at a speed comparable to compiled simulation.
Results showed that a cache as small as 4K instructions could provide
95% of the performance of a compiled code simulator, or five times the
throughput of an interpretive simulator with no loss of application
The third presentation, given by Michael Perrot from M.I.T., addressed
some of the problems of efficiently simulating frequency synthesizers.
Accurate simulation of quantization noise in a fractional-N PLL requires
an event-driven simulator whose time resolution is small compared to
the VCO period. This combined with the long time constants of the control
loop lead to unreasonably long simulation times. Perrot described two
techniques that would allow fast simulation based on a uniform time-step.
The first uses a constant signal-time area approximation to model the
continuous time behavior of the phase detector with a uniform time-based
sequence. The second models the VCO and divider as a single phase generating
block that can be accurately modeled at the reference frequency rather
than the much higher VCO frequency. Perrot went on to describe the simulation
of a second order 1.8-GHz synthesizer. Simulations of phase noise over
5 million samples yielded results closely matching measurement, yet
took only 80 seconds on a Pentium-a speed increase of two orders of
magnitude over conventional techniques.
In the final presentation, Walter Daems from Katholieke Universiteit
(Belgium) described a new technique for automatically generating posynomial-based
models of analog circuits from numerical SPICE simulation data. Component
sizing is an important step in analog synthesis. Posynomial expressions
of circuit behavior allow the modeling of linear and non-linear analog
behavior in such a way that component sizing can be formulated as a
geometric program. In the past, these posynomial models have been generated
manually. Daems described a direct fitting algorithm that has the advantage
of generating sparse models-models in which most of the coefficients
are zero. Experimental results with a CMOS transconductance amplifier
generated a model accurate to within 1% in a matter of minutes on a
network of 16 UNIX workstations.
The 40th DAC will take place 2-6 June 2003 in Anaheim, California. For
more details see www.dac.com.
SSCS AdCom Member
DAC Past Chair