A JSSC Classic Paper:
Low-power CMOS Digital Design
A JSSC Classic Paper
This article is one of a series on the most frequently cited papers
from the JSSC according to The Journal Citation Report-Science
Edition. "Low-power CMOS digital design" by A. P. Chandrakasan,
S. Sheng, and R. W. Brodersen originally appeared in April 1992.
It is the second most frequently cited in the history of JSSC
and is still the most recent paper of any frequently cited from
Why the paper was important?
At the time of publication, the switching speed and silicon area of
digital CMOS circuits were the primary design metrics used for circuit
optimization. This paper brought significant awareness to design techniques
that also allowed the minimization of power and energy required to perform
a given computation. It identified that, in order to minimize power
dissipation, the problem needed to be attacked at all levels of the
design process starting from the system level, through the architectures
and circuits, down to the underlying fabrication technology. Energy-optimized
design has now become one of the dominant considerations in CMOS design
with the ever-increasing importance of battery-operated devices and
the limitations of heat removal in high-performance systems.
What was its impact?
The most significant impact of this paper was identifying the emergence
of energy efficiency as a key metric in digital system design. Results
from fabricated test circuits validated energy models and identified
the key criteria to impact energy dissipation. The paper validated energy
models with voltage scaling and presented the effect of circuit style
selection, transistor sizing, and architectural optimization on energy
The architectural voltage scaling approach (in which hardware concurrency
is used to compensate for reduced throughput at lower voltages) demonstrated
the ability to improve the power-delay product by an order of magnitude
without performance loss and thus provided significant improvement over
traditional scaling approaches. The notion of using the power supply
voltage as a "free variable" met with significant skepticism
when the results were first presented at workshops and at the VLSI Circuits
Symposium Plenary Session. The paper solidified many of the concerns
with voltage scaling and validated results with circuit demonstrations.
The idea of trading-off silicon area for lower power has been used widely
in academia and in industry. The techniques also have been implemented
in academic and commercial CAD tools.
What inspired it and/or led up to writing
A large research program was underway (the Berkeley InfoPad project)
to develop a portable multimedia device that supported speech recognition,
video compression and decompression, pen input, and wireless communication.
It quickly became evident that the required functionality could not
be supported with a reasonable battery weight using traditional design
approaches. Before developing the electronics for the InfoPad terminal,
we decided to go back to basics and evaluate the fundamental sources
of power dissipation. This included analysis of computational fabrics
(dedicated logic vs general-purpose computing), components of power
in CMOS logic gates (switching vs short circuit vs device leakage),
and partitions between different modules (memory vs logic vs interconnect).
Our goal was to identify opportunities for making a dramatic impact
on energy efficiency rather than the incremental ones achieved by tweaking
circuit styles or process scaling. We saw a major opportunity at that
time, as there was a significant industrial push towards portable computing
and communication devices.
How useful is the information today?
Power and battery life continue to be critical concerns with the increasing
use of portable devices. In particular, in the wireless area there is
a constant push towards higher functionality and bandwidth at the lowest
possible energy consumption. Power also has become a major issue in
non-portable applications such as high-performance computer servers
in which the highest performance systems are now entering an era of
The paper provided the framework for energy to be considered as a primary
design criterion (rather than as an afterthought) with a focus on optimization
of the supply voltage, which has become a common strategy in present-day
While some of the parameters have changed (e.g., device leakage and
interconnects have become important considerations), the basic trade-offs
of energy and performance outlined in the paper still apply. The key
message in the paper is to take a system view of energy dissipation
that cuts across many traditional boundaries rather than simply rely
on process technology to solve the problem.
Bob W. Brodersen
Elected AdCom Member
The original paper is available on the Solid-State Circuits Digital
Archive 2002 DVD at www.sscs.org/Archive
(IEEE product # JD3755B); or link to the article in IEEE Xplore®
through JSSC Classics icon at http://sscs.org/jssc.htm.
See "So Many Articles, So Little Time."