Table 1. Overview of Events.
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The collection of papers by leading world experts to be presented at the International Solid-State Circuits Conference 2001 (ISSCC) 5–7 February 2001 at the San Francisco Marriott provides an extensive overview of achievements in the Internet Age (see Table 1). The Internet Age is a direct result of the tremendous advances in solid-state circuits enjoyed over the last three decades. Its impact is revolutionary in terms of cost-effective delivery of new products and services. The convergence of wireless and wireline digital communications with advanced computing technologies enables new System On A Chip concepts, apparently limited only by the imagination of the designers. The three plenary speakers support this theme:
Table 1. Overview of Events.
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i-mode mobile telephone services in Japan feature browsers that read HTML and send and receive email or obtain information from the Web. Of the 60 million mobile phone users in Japan, which is more than the number of fixed phone subscribers, 12 million have subscribed to i-mode in its first 18 months. In the future, i-mode will evolve into mobile multimedia and will feature Java technology, Secure Socket Layer (SSL) functions, and in the third-generation era of IMT2000, image transmission will become a reality. The key to i-mode evolution is processors that handle audio signals and execute a variety of applications. The author will discuss the status and future of i-mode services and their impact on IC technologies.
Driven by deregulation, a multitude of new transmission technologies has been deployed and standardized in recent years. Complex evolving standards require architectures with programmable DSP cores, standard processors, and memories complemented by downloadable software. New structures for analog drivers, power amplifiers, ADCs, and DACs are required to achieve transmission performance at reasonable power. Design is dominated by analog aspects. Achieving transmission performance with reasonable power consumption needs to be tackled by new structures for analog drivers, power amplifiers, ADCs, and DACs. Three families of access technology will be discussed: DSL, best known of the broadband technologies and outpacing the others in deployment speed; wireless in the local loop (WLL) and local multipoint distribution system (LMDS); and point-to-multipoint optical (PON), offering large bandwidth.
Continued advances in computer-system performance and power management will require innovations in all aspects of the computing platformÑarchitecture, microarchitecture, bus memory, and I/O performance. Mobile, desktop, and server platforms, as well as networking processors, will each have its unique metrics that drive performance improvement, enabling such applications as media-rich communications, computer vision, and speech recognition. Today's data-based, machine-based computing paradigm will evolve into tomorrow's knowledge-based, human-based computing, as the Internet becomes more integral to businesses and consumers.
TutorialsAttendees may register for a maximum of three tutorials. Topics are:
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During ISSCC 2001, 166 papers will be presented in 26 sessions. Following are some highlights selected in part by session Chairs. These and other related topics will be discussed at length at the ISSCC, the foremost global forum for new developments in the integrated circuit industry. More complete details are available at the conference Web site: www.isscc.org/isscc.
Session 3 on Monday afternoon and Session 8 on Tuesday morning will have presentations demonstrating the continuing shrinkage of ADC power supplies. All the data converters reported use 3.3 V or less; a bandpass sigma delta ADC implemented by V. Cheung et al. requires only 1 V. In separate papers, M. Choi and G. Geelen will report on 6-b CMOS ADCs that top 1 Gsample/s. Closing the conference on Wednesday afternoon during Session 23, N. Krishnapura and Y. Tsividis will present an analog lowpass filter that shows 112-dB input range, and H. Wand will report on a 50-GHz VCO fabricated in 1.3-V CMOS.
In Session 15 on Tuesday afternoon and Session 20 on Wednesday morning, three processor designs will be presented that achieve clock rates in excess of 1 GHz (see Table 2).
Table 2: Trends in Processor Frequency and Integration at ISSCC 2001. |
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In Session 6 on Monday afternoon, there will be seven papers presented that show the rapid innovations in CMOS imager and sensor designs, including embedded image processors. Session 16 on Tuesday afternoon will introduce microsensors of multiple functions integrated with on-chip interfacing and control electronics.
Rapid advances in flash and ferroelectric memory technology have yielded two significant results, to be presented this year at Session 2 on Monday afternoon. T. Cho et al. will report on a 1Gb NAND flash memory with 2b/cell in 0.15 µm CMOS which can be changed to 512Mb 1b/cell using fuses. Simultaneous operation of 4 independent banks results in 1.6 MB/s program throughput. Takashima et al. will present an 8-Mbit chain FeRAM in 0.25-µm CMOS with 40-ns random access time and 70-ns cycle time. On Wednesday afternoon during Session 24, H. Yoon et al. will present the world's first 4-Gbit DRAM made of 4 billion transistors in 0.10-µm technology with low-voltage operation.
New levels of integration have been achieved for multimedia systems with the addition of embedded DRAM. Designs for MPEG and graphics rendering are scheduled for Tuesday morning's Session 9 and a DVD system during Session 12 in the afternoon. On Wednesday morning, Session 21 will include a presentation on the first chips to support the 54-Mb/s IEEE 802.11a Wireless-LAN Standard and a complete set top box System On A Chip (SOC) that integrates a cable TC transceiver; an MPEG-2 decoder; a 2D/3D graphics processor; and all A/Ds and D/As for QAM/QPSK, audio, and video.
Fabrication of flip-flop and clock circuits in bacterial cells, called a genetic circuit, demonstrates a basis for future biochemical-based control circuits that operate inside a living cell. T. Gardner will discuss genetic applets Tuesday morning in Session 7. On Wednesday morning in Session 17, J. Burns et al. will describe three-dimensional ICs for low-power, high-bandwidth SOC. The circuit implements a back-illuminated 64 x 64 active-pixel sensor with fully parallel A/D conversion.
Bluetooth designs lead off the Wireless LAN papers in Session 13 on Tuesday afternoon, with other standards implementations for wireless consumer applications also presented. Of note are an IEEE 802.11-b single-chip transceiver, a 22-Mb/s zero-IF transceiver for a 2.4-GHz WLANs, and a 5-GHz CMOS WLAN receiver. For WCDMA implementations, attend Session 18 on 3-G wireless on Wednesday morning.
This year features ICs for gigabit optical communication at 10 Gb/s and 40 Gb/s. Advances in silicon CMOS and SiGe BiCMOS have now reached the point where SONET circuits can take advantage of these low-cost processes. With the higher levels of integration enabled, CMOS in particular can be expected to incorporate framing and coding circuitry to reduce package count. Over time, long-haul telecom systems will increasingly approach datacom systems in both cost and density. Six presentations are scheduled on Monday afternoon for Session 5 and seven more on Wednesday morning for Session 19.