ICs for Information Technologies, ISSCC 2002

Our lives have been, and continue to be, affected dramatically by the multitude of portable and table-top devices created for improved communications. We constantly are informed about news events, the stock market, and whoever or whatever we want to focus on. Information has become a commodity for many of us. This is a result of the new ICs that have been conceived and developed by the IC community to provide ever-growing capabilities at increasing speed and performance. As in other years, ISSCC 2002 provides the best available overview of the new ICs that have emerged this year, and that are destined to influence current and future markets.

The International Solid-State Circuit Conference will be held 3-7 February 2002 at the San Francisco Marriott Hotel. Tutorials, a workshop, and special evening sessions are available on Sunday, 3 February 2002. [ see schedule ]

Plenary Speakers

Three invited papers will begin the Plenary Session Monday morning. Dennis Buss, Vice-President, Silicon Development, Texas Instruments, Dallas, Texas, will talk about “Technology in the internet era.” In his view, internet electronic products, not PCs alone, drive IC technologies. Internet products need less computational power than PCs but better portability and cheaper cost to penetrate mass markets. SOCs will integrate everything including radio and wireline drivers, and Moore’s law will continue for another decade.

C.G. Hwang, CEO, Samsung Semiconductor Memory Division, Yongin-City, Korea, will speak on “Semiconductor memories for IT.” He feels servers will continue to drive high-density DRAMs with 16-Gb DRAMs expected this decade. Now memory is driven by graphics and networking applications. Low-power memory is driven by 3G phones and PDAs. He also believes Moore’s law will continue for another decade.

Fred Boekhorst, Senior Vice-President, Philips Research, Eindhoven, Netherlands, will talk on “Ambient intelligence: The next paradigm for consumer electronics.” Ambient intelligence refers to an environment where the user experience is what matters. People want to have fun, to be in control, and to be productive. This is not linked to one particular device but a network of on-body devices that allow new experiences. The three driving directions are radio, user interface, and visual display.

Contributed Paper Sessions

The Program Committee evaluated over 350 papers submitted from around the world and selected 171, with authorship equally divided among the United States, Europe, and the Far East. Over three-quarters of the presentations are industry papers with one-quarter from Universities. The papers are grouped into eight major topics and presented over three days in 25 sessions with five simultaneous sessions. Registrants may look for these and other highlights as they examine their Advance Program, available on-line at www.isscc.org.

Analog

Session 10 on Tuesday morning will unveil an 8-bit ADC operating at 4 Gigasamples per second, a 20-fold increase in sample rate. Surprisingly, this result has been achieved in 0.35µm CMOS. Formerly, such performance was available only in the realm of expensive processes such as SiGe and GaAs. This ADC will provide a critical jump in the performance of lead-edge test equipment.

In Session 18 on Wednesday morning the lowest-ever voltage supply to power an Sigma-Delta ADC will be reported at 0.7 V. Normally ADCs switch the filter capacitors and require 1.5 V. This ADC design switches the entire operational amplifier, which allows the lower supply voltage. Conventional CMOS processing can be used and the filter capacitors are provided by the inherent capacitances of the transistors themselves.

Session 23 on Wednesday afternoon introduces, for the first time, a disposable chip for hearing aids. It utilizes many low-power, low-voltage analog-circuit techniques and provides 40 days of average use with a small zinc-air battery.

Digital

With four sessions on digital topics, there will be coverage throughout Tuesday and Wednesday. Attendees will hear about the introduction of 0.13µm technology in product roll-outs of the next-generation Power PC in Session 8 on Tuesday morning and Ultrasparc in Session 20 Wednesday morning. Technology trends in extending microprocessor performance are also evident in the move to body-bias solutions which reduced standby power in one CMOS communications router by a factor of 3.5. Body-bias is proposed in numerous papers, in particular during Session 16 on Tuesday afternoon and Session 25 on Wednesday afternoon.

With the scaling of silicon-process technology confronting fundamental limitations, more pressure is being focused on the means of achieving performance beyond simply increasing frequency. Primarily this is achieved by getting the microprocessor to do more per clock cycle. For example, in Session 8 on Tuesday morning there are two reports on clock-distribution systems for centimeter-square-sized die with skew reduced below 25 ps. In addition, several papers highlight the latest chip system organizations, including huge and complex on-chip caches, expanding banks of execution units, and multi-threading. For example, Session 20 on Wednesday morning will report the latest superscaler multithreaded Alpha processor with 2.5 to 3 times the performance of previous generations using over 3 MB of on-chip cache.

Embedded designs for System-on-a-Chip building blocks that will be presented during Session 20 on Wednesday morning are characterized by a device count of approximately 5 million transistors, die sizes of under 75 mm², and power consumption of no more than 0.5 watts. Performance will be shown to reach 400 MHz. This kind of performance represented the best-of-breed processor performance less than 5 years ago!

Imagers, Displays, and MEMS

Session 2 on Monday afternoon will focus on adding functionality to both CMOS and CCD devices, rather than the usual pursuit of larger chip size, higher resolution, or greater image quality. With sensors there is little sense of the “traditional” CMOS vs CCD arguments as CMOS and CCD sensors have each found their own niche application areas. CCD sensors continue to add functions in order to remain competitive in a world of low-cost CMOS devices threatening their dominance of the digital still-camera market.

Session 26 on Wednesday afternoon will focus on the interface between the ‘real’ world and the ‘digital’ world. The signals vary from mechanical (in accelerometers and gyroscopes), to chemical (in volatile-organic compound sensors), to thermal (in wind monitors), to light (in imagers and displays). Micromachining technologies are used to realize sensor elements that could not be implemented using conventional IC technology. This session will report the first fully functioning solid-state micromechancial gyroscope. This compact industrial-quality system incorporates a large number of on-chip signal-processing circuits along with mechanical parts. The world’s first organic light-emitting microdisplay (OLED) on silicon will also be reported. This low-power color display will enable such systems as head-mounted displays and other near-to-eye implementation such as ‘Dick Tracy’ watches.

Memory

Session 6 on Monday afternoon will report the first 1-Gb 1-bit-per-cell NAND Flash memory. High-density general-purpose memories expand across broad applications providing lower-cost, higher-density non-volatile mass storage.

Session 9 on Tuesday morning will show the highest-density ferroelectric memory reported to date. The 8 Mbit barrier in ferroelectric memory has been broken by a 3.0-V 32 Mb FeRAM, implemented for static data storage in a 0.25µm process. The reported density gives FeRAM a competitive edge compared with SRAM, which has peaked at 16 Mbit density. The memory implements an SRAM-like asynchronous interface by using address-transition detection to generate internal clock signals. SOI technology is also shown to offer smaller, more efficient DRAM cells with non-destructive read capability.

Signal Processing

The deployment of advanced wireless systems and continuing ad-vances in storage density and bandwidth necessitate similar advances in digital signal processors and circuits. In Session 3 on Monday afternoon the first 10-Gb switching processor for high-speed internet will be introduced. Also, two out of three high-performance DSPs for 3G wireless base-stations will be described in this session; look for a third 3G device during Session 7 on Tuesday morning. A two-chip IEEE802.11a solution will also be presented.

A variety of multimedia devices will be presented in Session 22 on Thursday afternoon, covering 3G and MPEG4. The three lowest-power video codecs in active and standby mode will be presented for portable applications. They use a high level of circuit integration and relatively low clock speeds to reduce power consumption.

Technology Directions

In Session 12, Digital Directions, several emerging technologies that could reduce costs and lower the power consumption of future digital designs will be presented. A supercomputer System-on-a-Chip project will be described. Using energy-efficient and area-efficient embedded-processor cores, it becomes possible to place two processors plus the upper three levels of the memory hierarchy on a single chip. This chip can be arrayed to build a supercomputer containing hundreds of thousands of processors with cost and power consumption much lower than a design based on conventional desktop and server microprocessors.

Ovonic technology, previously used mostly for solar-energy conversion, will be combined for the first time with conventional CMOS to yield a dense, fast, low-voltage non-volatile 4 Mbit memory. It stores information as a phase change between amorphous and polycrystalline states, similar to the technique in rewritable CD and DVD technology. Also in this session, on-chip global diagonal routing is demonstrated on a 128-bit RISC processor that shows a 19.8% path-delay reduction and a 10% area reduction.

For the past few years ISSCC has been the primary venue for presenting the latest developments in highly integrated ICs for fingerprint sensing and analysis. Session 21 on Wednesday morning will report two papers describing single-chip integrated solutions for low-cost high-volume markets, such as consumer fraud prevention and security. Remote sensing of vital signs with a fully integrated direct-conversion Doppler radar for noninvasive detection of heart rate and respiration will be reported in combination with its 1.6-GHz transceiver. Very exciting developments in the field of bioMEMS and DNA analysis chips also will be reported in this session: a 16X8 DNA sensor array with a fully-electronic readout scheme on top of a standard DMOS chip without the need for optical components will allow low-cost and high-performance fabrication.

Wireless Communications

Session 5 on Monday afternoon will feature several outstanding presentations in the areas of Bluetooth integration and cost reduction as well as IEEE 802.11a, the newest of the deployed wireless-LAN technologies. The first fully integrated 802.11a radio will also be presented in this session.

Presentations on cellular telephone RF functions on a single IC (excluding power amplifiers) are scheduled for Session 14 on Tuesday afternoon. Several state-of-the-art advances in integration, improvements in performance levels, and additional functionality will be reported. An example is a cellular RF chipset with an added GPS receiver.

Advanced RF techniques, on Wednesday morning in Session 17, presents a number of solutions to the integration challenge of the VCO due to phase-noise issues. Also at this time look for startling advances in integration of systems operating in excess of 50 GHz. There is an IC wireless transceiver handling data at optical-fiber rate speeds (1.25 Gb/s) in a wireless environment. Operating at a data rate of 1.25 Gb/s at a frequency of 60 GHz, it uses a band which is 25 times higher in frequency than Bluetooth or other popular LANs. A fully integrated VCO at 51 GHz using low power will also presented. Using standard 0.12µm CMOS technology, this device will support wireless portable handsets in band enabling these wide 1 Gb/s data rates.

All the papers in Session 24 on Wednesday afternoon will demonstrate the growing acceptance of CMOS as an RF technology because of its ability to provide acceptable RF performance at low cost, as well as its amenability to integrate with digital blocks. A highly integrated broadband cable-tuner IOC in 0.35µm CMOS and a single-chip CMOS GBS receiver with the lowest power consumption to date will be presented.

Wireline Communications

To satisfy the increasing demand for backplane interconnect bandwidth, papers on serializer/deserializer (SerDes) technology in Session 4 on Monday afternoon will show significant improvements on several fronts, namely power consumption down to 86-mW per SerDes channel, unprecedented integration, and reduced jitter.

Tuesday afternoon’s Session 15 will present papers showing how optical communication systems continue to move towards 10- to 40-Gb/s rates. Prior 10-Gb/s SONET required GaAs or SiGe ICs, which increased system cost and complexity. Low-cost 10- to 40-Gb/s Ethernet datacom systems now match the data rate of OC 192 SONET telecom systems. SONET survival requires aggressive cost reduction in SONET system designs. The novel contributions stepping up to that challenge are the first fully-integrated OC-192 transmitter and receiver realized in standard 0.18µm CMOS. The highest bit-rate ever reported for 4:1 MUX and 1:4 DEMUX circuits in 0.2 micron SiGe BiCMOS will enable >50 Gb/s optical systems. New techniques for implementation of 10-Gb/s CDRs for SONET OC-192 and DM applications will improve jitter and enable use of lower-cost technologies.

VDSL technology is expanding the DSL bit rate by an order of magnitude for short-loop applications. Wednesday morning’s Session 19 will feature two different approaches on architectures and circuits for low-power central-office line drivers for Discrete-Multi-Tone (DMT) ADSL, taking advantage of a high-performance trench isolated complementary-bipolar process. This session will also describe the first two published implementations of the analog-front-end ICs for the recently adopted DMT-based 4-band VDSL standard. This standard specifies up to 12 MHz of analog bandwidth and partitions the spectrum into two downstream bands and two upstream bands. Note that both implementations require external line drivers and other external line-interface circuitry.

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