Retrospective on the 2001 Symposium on VLSI Circuits

The 2001 Symposium on VLSI Circuits was held 14-16 June in Kyoto, Japan. The Symposium covered all aspects of transistor-level design including memories, multimedia networking, data transmission, and design optimization. This year there were 431 attendees from 16 countries. A record 76 papers were presented, chosen from 153 submissions. Particularly exciting this year was the unprecedented increase in papers presented by students from colleges and universities. Many of these papers were selected by the Session Chairs to be the highlighted papers for the Symposium. In spite of the recent difficult economic times, the Symposium has experienced increased attendance over each of the last three years. This, together with the surge of high quality university papers, is a very positive sign for the future.

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Attendees at the VLSI Circuits Symposium receive instruction in traditional wireless communications from the Gion Taiko Group.

Those attending the Symposium were afforded the opportunity to attend a memorable Short Course on low-power microprocessors, take part in a number of interactive rump sessions, and listen to presentations covering novel and leading-edge concepts in communications, memory, analog circuits, and display electronics. On the final night of the Symposium attendees received a taste of local culture with a demonstration, audience participation included, by the Gion Taiko group.

As is our annual tradition, the Symposium on VLSI Circuits is held in conjunction with the VLSI Technology Symposium. Having these two symposia together affords opportunities for engineers and scientists from many nations in technology and circuits/systems to interact. This year the interaction was highlighted by our joint rump session “Which features of an IC technology will benefit radio system on a chip?” The rump session succeeded in bringing together a broad range of expertise to discuss the main technology features required to minimize cost and power of hand-held devices in this potentially huge market. The rump sessions at the 2001 Symposium were found to be exciting and stimulating, as evidenced by the consistent high attendance throughout the evening.

The day prior to the Symposium, M. Matsui of Toshiba and Greg Taylor of Intel set the high standard for this year by organizing a very topical one-day Short Course on the “Physical design for low-power and high-performance microprocessor circuits.” Each presentation in this exciting course featured speakers, who are the leaders in their field, teaching others how to do what they do best. The course started off with J. Moench of AMD describing the “Interconnect design of Athlon™ microprocessors” and was followed by K. Ishibashi of Hitachi presenting “Substrate-bias techniques for SH4.” The afternoon started with C.T. Chaung of IBM discussing “High-performance SOI digital design — from devices to circuits,” followed by H. Takahashi of Texas Instruments teaching about “Low-power and high-performance circuit design of general-purpose DSPs.” S. Miyano of Toshiba taught about “Embedded DRAM SOCs and its application for MPEG4 Codec LSIs,” and L.T. Clark of Intel punctuated this very successful Short Course with his presentation on “Circuit design of Xscale™ microprocessors.”

Each of the first two days of the Symposium started with invited talks. M. Ishikawa and T. Komuro of the University of Tokyo presented a paper on “Digital vision chips and high-speed vision systems,” while Chenming Hu of the University of California, Berkeley, summarized years of outstanding contribution to the industry in his talk on “BSIM model for circuits using advanced technologies.” On the following day, K. Yoneda et al. of Sanyo Electronics presented “Development trends of LTPS TFT LCDs for mobile applications.” Peter van Kessel of Texas Instruments followed with his presentation on “Electronics for DLPTM technology-based projection systems.” The latter quietly substituted his palm-sized projector for a 50-kg auditorium projector and, with a flair for theatrics, revealed this to the audience at the end of presentation.

The strong tradition of memory papers was highlighted in this year’s Symposium by papers addressing a broad cross section of technical issues. “A bit-line GND sense technique for low-voltage operation FeRAM” was presented by S. Kawashima et al. of Fujitsu. In addition, D. Takashima et al. of Toshiba reported their work on “A cell transistor scalable array architecture for high-density DRAMs.” Closing out the memory presentations was M. Yamaoka et al. of Hitachi who reported their work on “A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit.”

Low power at higher performance has been an emerging theme of the VLSI Circuits Symposium and this year we had a variety of strong contributions. “A sub-130nm conditional keeper technique” was reported by Ram Krishnamurthy et al. of Intel. S. Kim et al. of the University of Illinois, Urbana-Champaign, reported on “A low-swing clock double-edge triggered flip-flop.” In addition, Ram Krishnamurthy et al. of Intel described their work on “A 0.13-µm 6-GHz 256x32b leakage-tolerant register file.” Explaining how to provide just enough power for the application, J.Kim and M. Horowitz of Stanford University presented “An efficient digital sliding controller for adaptive power supply regulation.” Finally, the concepts of leakage current reduction were presented in “A 63-µW standby-power microcontroller with on-chip hybrid regulator scheme” by M. Hiraki et al. of Hitachi.

The future of wireless was well represented by three strong papers from the academic community.

“A 15-GHz wireless interconnect implemented in a 0.18-µm CMOS technology using integrated transmitters, receivers, and antennas” was presented by B. A. Floyd et al. of the Univeristy of Florida. A paper by Y. Koo et al. of Seoul National University described “A fully-integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems.” Finally, S. Mahdavi and A. A. Abidi of UCLA reported their work on a “Fully integrated 2.2-mW CMOS front-end for a for a 900-MHz Zero-IF wireless receiver.”

The strong tradition of high-quality analog papers in the Symposium was represented by a truly global collection of featured papers. “A 1.57-GHz fully integrated very low phase noise quadrature VCO” was reported by P. Vancorenland and M. Steyaert of ESAT-MICAS, Belgium, and “An optimally coupled 5- GHz quadrature LC oscillator” was presented by P. van de Ven et al. of Phillips Research Laboratories and Eindhoven University of Technology. In the area of converters, A. Shabra and H.S. Lee of the Massachusetts Institute of Technology discussed their work on “A 12-bit mismatch shaped pipeline A/D converter.” From Matsushita, T. Morie et al. reported “A 200-MHz 7th-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-µm CMOS process.” Rounding out this fine collection of analog papers was “ A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range” by T. Yamaji et al. of Toshiba.

We hope you will join us this June in Honululu, Hawaii, for the 2002 Symposium on VLSI Circuits so that you may experience all aspects of the Symposium.

David Scott
2002 Symposium on VLSI Circuits Chair

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