ISSCC
Focuses on Power Management
ISSCC 2003 in San Francisco, California,
9-13 February, will introduce major breakthroughs in a broad spectrum
of cutting-edge wireless and portable products. The conference theme this
year is Power-aware systems.
Power-aware design methodologies have become a major concern with the
increasing use of portable multimedia and wireless devices as well as
non-portable applications such as high-performance computer servers. End
users continue to demand higher functionality and bandwidth, without the
requirement of being attached to a fixed power source. Operating from
scavenged energy and requiring extreme power management are new and exciting
wireless applications using distributed sensor networks for medical monitoring
and security.
System-level methodology addresses the energy efficiency of sensing, computation,
and communication. Power management improvements come from modifications
to the underlying process technologies, innovative mixed-signal circuits,
new computation/communication architectures, and the actual improvement
of energy sources.
Power-aware design methodologies are highlighted in the Plenary Sessions,
in five of the nine evening sessions, in three of the four workshops,
in two of the seven tutorials, the Thursday Short Course System-On-a-Chip
Design, and in nine of the twenty-five technical paper sessions. Look
for thePA indicator throughout
this article.
Register at www.isscc.org/isscc.
Articles from the Digest will be available in IEEE XploreTM
by early summer.
Plenary Speakers
Gordon E. Moore, Chairman Emeritus of the Intel Board, will open the Plenary
Session of ISSCC Monday morning with No exponential is forever: but forevercan
be delayed! Musing that the number of transistors produced each year has
grown by eight orders of magnitude in thirty years, Moore will review
how the law named after him has been applied to many metrics in the semiconductor
industry, such as processor clock performance, number of transistors on
a die, and world-wide revenue. However, several issues can limit this
exponential growth, including processor power dissipation, integration
complexity and verification, and complexity and cost of emerging device
structures. At least another decade of device, circuit, and architecture
innovations will continue exponential growth.PA
Takayasu Sakurai, University of Tokyo, will focus on one of these limits
with Perspectives on power-aware electronics. Device leakage is dramatically
increasing with technology scaling. Innovative leakage mitigation techniques
will be required to achieve long system battery lifetime, and energy efficiency
is a critical metric in battery-operated and self-powered electronic systems.
To address the power problem, Sakurai takes a systems view that requires
cooperation between circuit/device techniques and system software.PA
Bruno Murari, STMicroelectronics, Cornaredo, Italy, will present Interfacing
electronic systems to the external world. While there has been a huge
increase in the computing power of digital circuits, there has not been
a similar evolution in circuits that interface to the external world.
Murari holds that low-voltage CMOS is inadequate for interface applications,
and emphasis must be placed on BiCMOS, HVCMOS, and BCD. System-On-a-Chip
and System-In-a-Package technologies will enable integration of MEMS and
photonic technologies with conventional electronics.
Evening
Special Topic Sessions
Evening Special Topic Sessions provide a range of treats primarily for
the benefit of attendees, as they are not documented in the conference
Digest. Starting before the traditional weekday opening, Sunday evening
will have three sessions. the first will highlight four prime technical
presentations from the Design Automation Conference. At the second Ian
Young, Intel, will chair Circuits for emerging technologies, featuring
a range of five specific circuit techniques for high-performance microwave
frequencies and giga-scale ICs that may emerge as the right match with
fabrication process technology. Finally Trudy Seltzer, TI, will chair
Integration for 3G Cell Phones, which features four speakers on trends
and tradeoffs in baseband and RF sections of the 3G system.
Weeknight Evening Special Topic Sessions will tend toward the more freewheeling
controversy-based panels on a specific application or challenge. Half
a dozen experts will volley back and forth with a moderator keeping the
ball in play.
Analog
Monday afternoons Session 3 on oversampled converters will feature a number
of continuous time modulators that set new records for low power at high
performance. It also provides the first triple mode modulator for cellular
phones, presented by R. van Veldhoven, Philips Research, Eindhoven, The
Netherlands.
Tuesday mornings Session 7 on DACs and AMPs will provide a variety of
analog and mixed-signal circuits pushing dynamic range and speed. W. Schofield
et al., Analog Devices, will demonstrate a 16-bit DAC producing high-dynamic
range signals at 300 MHz output frequency. This is a major advance for
signal generation with linearity sufficient for upcoming wireless applications,
at -80 dBc intermodulation distortion.
Wednesday mornings Session 18 on Nyquist ADCs will open with a CMOS circuit
by K. Poulton et al., Agilent Laboratories and Agilent Technologies, that
pushes the parallel pipeline out to the lunatic fringe, sampling at 20
GS/s with an 8-bit resolution.
Wednesday afternoons Session 23, Mixed-signal and wireline technologies,
will present an unusual very-low-power technique. S. Ranganathan and Y.
Tsividis, Columbia University demonstrate that a voltage sampled on the
gate rises when the channel charge is pulled out. By varying the operating
region of a MOSFET, its small-signal capacitance changes. Based on the
40-year-old idea of the parametric amplifier, noise-free amplification
is implemented.
Digital
Session 6 on Monday afternoon will focus on the conference theme of power
aware systems. J. Tschanz et al., Intel, will present a multifaceted approach
to controlling transistor leakage power for an integer ALU. Using sleep
transistors, active body biasing, and conventional clock gating, this
work studies the idle time required to achieve power savings. A minimum
required idle time is reported that is needed to reduce leakage during
the idle periods and increase the performance of the part during active
periods.PA
Session 14 on Tuesday afternoon will present continued advances in microprocessor
integration and computation power, resulting in chips with over 400 million
transistors and processor components operating at 5 GHz. H. Ando et al.,
Fujitsu, will introduce the 1.3-GHz 35-W SPARC64 built with 130-nm CMOS
process and eight layers of Cu metallization. J. Stinson and S. Rusu,
Intel, will introduce a third generation 64-bit Itanium processor, operating
at 1.5 GHz.PA
Clocking circuit design in microprocessors show notable advances in two
sessions. N. Bindal et al., Intel, will present a multi-GHz processor-clock
of three-level distribution design for the next generation of Pentium
processors, with less than 10 picoseconds of skew, on Wednesday morning
in Session 19. On Wednesday afternoon in Session 24, R. O'Mahony et al.,
Stanford University and Atheros Communications, will present a novel prototype
concept, a 10-GHz clock distribution with less than 1 picosecond of skew
using coupled standing-wave oscillators.
Imagers, Displays, and MEMS
Wednesday mornings Session 11 will feature a number of advances for the
biomedical industry. N. Manaresi et al., Silicon Biosystems and University
of Bologna, Italy, will present a CMOS chip that detects and manipulates
more than 10,000 individual cells in parallel, useful for investigating
cell interactions for drug screening, cell separation, and cell analysis.
Later in the same session, M. Xue et al., Hong Kong University of Technology
and South East University, Nanking, China, will present a CMOS chip for
DNA identification.
Wednesday afternoons Session 12 will feature CMOS chips that embed analog
and digital circuitry to collect raw images and extract information about
fingerprints, neural signals, computational vision, and projection. I.
Takayanagi et al., Micron Imaging, Tokyo, will introduce a large-format
video camera chip, an 8.3 mega pixel sensor in CMOS that provides images
for ultra-high-definition television while consuming only 760 mW.
Memory
Memory papers will present breakthroughs in nonvolatile memories. In session
16, M. Crowley et al., Matrix Semiconductor, Santa Clara, California,
will open a new era in 3D memory architecture, fabricating eight layers
of memory planes above CMOS peripheral circuits, lowering cost. Only a
small percentage of the chip area (relative to other non-volatile memories)
is devoted to memory-cell construction. J. Lee et al., Samsung, Republic
of Korea, break records with the smallest yet NAND Flash cell, reporting
for the first time the use of 90-nm technology to produce 2 Gb of Flash
storage. With its low 1.8-V operation this technology expands new portable
mass-storage applications.
Signal Processing
Monday afternoons Session 2, New levels of integration for DVD processors,
will demonstrate that System-On-a-Chip designs are poised to play key
roles in effective solutions that meet cost, performance, and power constraints
for real-time digital video and audio for the consumer market. K. Okamoto
et al., Matsushita, embeds most of the building blocks for a complete
DVD player on a 64-mm2 die using only 1.5 W. A DVD decoder directly reads
the data channel and then interfaces directly to the video display and
the audio output channel. J. Geerlings et al., Phillips Semiconductors,
will present an integrated MPEG-2 video and audio encoder/decoder that
supports DVD+RW and digital video recording applications.PA
In Session 8 on Tuesday morning, D. Carlson et al., Cavium Networks, Santa
Clara, California, will present a security processor that provides the
most integrated and fastest SSL handshake available. Secure internet connections
are established via security protocols such as Secure Socket Layer (SSL)
and Internet Protocol Security (IPSEC). Later in the same session, several
power-efficient Turbo decoders will be presented for improved 3G wireless
devices to deliver high-speed data services via mobile cellular networks.PA
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Technology Directions
Session 9 on Tuesday morning will present technologies, systems, and architectures
for advanced computer designs, smart PDAs, and digital cinematography,
each integrating extremely complex systems onto a single device. Hugo
De Man et al., IMEC, Leuven, Belgium, and Alcatel, Antwerp, Belgium, will
discuss design methods to bridge the high- level system/software abstractions
of these complex systems and the physical and electrical models of the
chips.
Session 21 on Wednesday morning will showcase the new organic technologies
that offer the potential of new and ultra-low-cost applications, as well
as advances in silicon technology and devices. For example, E. Huitema
et al., Philips Research, Eindhoven, The Netherlands, will demonstrate
a display using plastic transistors with potential for future flexible
displays.
Session 22 on Wednesday afternoon will present key technologies to embed
for portable systems; power generation and power optimization technologies;
as well as on-chip and wireless communications technologies. Two thermogenerators
will be presented that convert body heat into electricity by finding or
creating temperature difference. S. Jung et al., Infineon Research, Munich,
Germany, will describe several technologies needed in the area of wearable
electronics, such as chips and antennas woven into smart clothing with
copper replacing fabric threads and again harvesting energy from body
heat. T. Douseki et al., NTT, Atsugi, Japan and Seiko, Japan, will present
a 100-mm thick RFID tag chip with front and backside contacts for attachment
to a dipole antenna; the tag chip can be fabricated on paper or fabric
media for wearing. M. Schmidt of MIT, Cambridge, Massachusetts, will describe
two MEMS-based devices that burn fuel to generate power as an alternative
to conventional batteries.PA
Wireless Communications
Session 5, Wireless PAN transceivers, on Monday afternoon will feature
several outstanding presentations in the areas of Bluetooth/802.11b integrated
transceivers, and performance and cost improvements for standalone Bluetooth
solutions. The first published 802.15.4 radio also will be presented by
P. Choi et al., KAIST Daejeon, Republic of Korea.PA
Presentations on cellular communications are scheduled for Session 15
on Tuesday afternoon. New circuits for WCDMA transceivers implementing
direct conversion will be presented. This session also features a fully
integrated direct conversion GSM-GPRS transceiver that provides GSM850/GSM/DCS/PCS
functionality, authored by E. Duvivier, Texas Instruments, Villeneuve
Loubet, France.PA
The initial adoption of Wireless Local Area Networking (WLAN) technology
has been sluggish. However, the recent demand in wireless networking in
public hot spots, enterprise networking, and home networking, together
with advances in IC technology enabling lower-cost integrated solutions,
have provided significant growth in the last couple of years. Session
20 on Wednesday morning will present a number of different solutions for
802.11a and 802.11b transceivers, as well as building blocks for future
developments in the wireless area.PA
The RF Infotainment Session 25 on Wednesday afternoon will demonstrate
several RFICs that are enabling new classes of entertainment and information
appliances. This session will feature several presentations on integrated
solutions for satellite, cable, and terrestrial tuners. The session also
will present a SiGe BiCMOS up-converter for cable head-end applications
for Video-on-Demand systems, as well as several building blocks for future
systems by K. Ashby et al., Microtune, Plano, Texas.PA
Wireline Communications
Monday afternoons Session 4, "Clock recovery and backplane transceivers",
will feature several advances in 3- to 10-Gb/s copper-link signaling.
Numerous high-density PC-motherboards and router backplanes will be presented
as well as high-speed inter-chip communications.
Tuesday morning's Session 10, "High-speed building blocks,"
will cover a wide range of topics on high-speed data transmission. H.
Wu et al., Cal Tech, Pasadena, California, and IBM Thomas J. Watson Research
Center, cut the cost of both SONET and 10-Gb Ethernet by using a CMOS
analog transversal filter to extend transmission distances on multi-mode
fibers. S. Gala and B. Razavi, UCLA, present one of two papers comparing
different 10-Gb/s laser drivers; they fabricated a 10-Gb/s limiting amplifier
and laser driver chip in 180-nm CMOS.
Tuesday afternoon's Session13, "Communicating at 40 Gb/s," will
describe the first ICs to meet the high-level industry standard for optical
systems. 40-Gb/s circuits are a reality in several technologies like SiGe,
CMOS, and InP. The first complete chipsets for OC-768 and SFI-5 standards
systems are moving into mainstream technologies like SiGe.
More for Registrants
A special event for registrants to enjoy at their leisure this year will
be full-length video interviews with five ISSCC pioneers, available on
one of the Marriott Hotel in-room TV channels. The interviews are part
of the 50th anniversary of the ISSCC, which was first held in 1954. Interviewed
were pioneers involved in the initial formation of ISSCC: Richard Baker
(MIT Lincoln Labs), Murlin Corrington (RCA), John Linvill (Bell Laboratories),
Arthur Stern (General Electric), and Jerry Suran (General Electric).
