ISSCC Focuses on Embedded Systems

ISSCC is the foremost global forum for presentation and discussion of new developments in the integrated circuit industry. The theme for 2004 is “Embedded systems for a connected world.” The intelligence in integrated circuits is attributable to their embedded microprocessors, and now they are used for every aspect of computing and control, including their own efficiency and performance. Memories (SRAM, DRAM, and Nonvolatile) are integrated in order to achieve higher performance, and/or lower power. Other imbedded functions include analog circuits, such as A/D and D/A converters, DSPs, RF CMOS and CMOS image sensors, and wireline communication interfaces. ISSCC 2004 will introduce major progress in embedded systems for wireless, wireline, and mobile applications.

Over 200 papers will be presented in twenty-seven sessions during the three days of the conference. What follows are a few highlights of eight major topics the conference covers.

To register for the 15–19 February conference in San Francisco California, or for a more detailed view of all the presentations in the Advance Program, go to www.isscc.org/isscc. Articles from the ISSCC 2004 Digest will be available in IEEE Xplore™ by summer.
Analog

2004 may be the year of the converter at ISSCC; this year will feature four sessions dedicated to new A/D and D/A converters! These papers will establish many new benchmarks for converter state-of-the-art in speed, resolution, power, and area efficiency.

Converters form the critical interface between “real world” analog signals and the digital signals processed by computers. As signal-processing systems become more sophisticated, the converters can become the bottleneck that ultimately limits system performance. Conversely, in some cases, converter advances can actually enable fundamentally new architectures.

In Monday afternoon’s Session 4 Philips Research (4.1) and ETH Zurich (4.2) will present converters that push sigma-delta-converter bandwidths to 10 MHz and beyond to handle next-generation broadband communication requirements. In Tuesday afternoon’s Session 14 National Semiconductor (14.1), will describe high-speed A/D converters that bring 1 GS/s performance into the mainstream. In Wednesday morning’s Session 20, Analog Devices will describe an IC that extends 14-bit D/A converters to sample rates beyond 1 GS/s to simplify multicarrier radio processing (20.1). This is another important step towards “software radio.” Multiple sessions will feature converter papers that wrestle with the challenges of integrating converters onto digital circuits implemented in deep-submicron CMOS technology (4.5, 14.5, 14.3).

In Wednesday afternoon’s Session 25 all the papers will highlight new algorithms to allow digital calibration of analog non-idealities in ADCs. Although calibration techniques have been used for more than twenty years, this session will feature the recent flurry of new development that helps lower power dissipation and enables operation at significantly reduced supply voltages.

Both foreground and background calibration techniques will be explored in various papers. In foreground calibration, the normal operation of the A/D converter is stopped while the converter goes through a “calibration cycle.” In background calibration, techniques are used to detect and correct converter errors during the normal operation of the converter. In some cases, techniques common to some of today’s spread-spectrum communications systems are applied to separate converter errors from the signal being processed by the converters. The result is a number of new high-performance A/D converters that can be efficiently realized in deep-submicron processes.

Digital
The past year has seen a number of microprocessor companies leverage their large investment in existing designs by shifting fabrication to faster, smaller-featured manufacturing processes. These provide millions of extra transistors, leaving microprocessor designers with the question of how to use these extra devices while avoiding significant redesign costs and escalating power concerns. Intel (3.4) will present design techniques to improve design productivity and reduce the cost of redesign.

IBM (3.1) and Sun (3.2) integrate multiple independent processor cores on one chip. Many important server applications, including Web hosting and databases, are already designed to divide their workloads into independent tasks, enabling these chip-scale multiprocessors to provide greater throughput by running multiple tasks simultaneously.

Designers must also address the static leakage of these extra transistors. IBM (3.7) and Sony (3.5) will present aggressive circuits that dynamically adjust voltage levels and frequency to lower power, while Sun (3.2) will introduce a novel circuit to offset a new reliability issue caused by advanced transistor technologies.

Session 8 on Tuesday morning will feature computing at ultra-low voltages. Lower power supply voltage typically requires lower voltage to turn on a transistor, called threshold voltage (Vt). Lowering voltage saves power consumption, but ultra-low voltage leaves processors vulnerable to increased noise sensitivity and lower computation speeds. Intel (8.4) will present a new technique that automatically reduces the (Vt) with supply voltage to provide better performance at very low power. STARAC (8.6) will show that the increase in noise problems for circuits at lower voltages can actually be actively suppressed by innovative circuits.

Wednesday morning’s Session 19 will focuse on multi-GHz clocking. Clocking generation and distribution with minimal differences in clock arrival times (skew) across the chip is difficult yet essential for state-of-the-art integrated circuits. However, clocking generation also consumes a large portion of the total power. Columbia University and IBM (19.1) have used on-chip spiral inductors that resonate with the clock capacitance and achieve a 35% reduction in clock power dissipation.

NEC (19.5) and IBM (19.7) provide on-chip skew-measurement circuitry to show a more realistic view of the clock-skew variation under normal operating conditions, minimizing future over-design.

Imagers, Displays, and MEMS
During Monday afternoon’s Session 6, Canon (6.1), Matsushita (6.2), and Sony (6.3) will introduce three developments in high-density CMOS imagers that increase pixel density on a sensor, decreasing sensor cost, and reducing the size and cost of the lens needed in the end application. Each design uses intelligent sharing of components and operation functions. All three use buried pinned photodiode structures to increase efficiency. One of the designs will report pixel pitch only nine times the minimum device dimension. Overall, these three papers will highlight significant trends in imaging for expanding low-cost consumer-product applications.

Tuesday afternoon’s Session 12 will introduce a neural prosthesis device for the restoration of sight to the blind (12.1). The group from UC Santa Cruz and USC has performed three human clinical trials with outstanding results. The blind patients were able to read large letters, count objects, and recognize and differentiate objects such as a cup and a plate. Next, researchers from Infineon (12.2) will describe DNA microchips with electronic readouts that offer potential competitive alternatives to optical detection of biochemical reactions.

On Wednesday morning re-searchers from Rockwell Scientific (17.1) will describe and display a microprocessor using micro-sized mechanical switches. Bulky discrete-circuit techniques are still required in ultra-high-frequency circuits; with MEMS devices operating within the integrated-circuit-scale environment, the situation has changed dramatically.

Later in the morning, researchers from St. Jude’s Medical Center (17.5) will report the highest level of integration in an interface IC for implantable cardiac pacemakers, enabling smaller size and increased lifetime.

Memory
Flash technology is now mature and is challenging the density leadership of DRAM technology. Samsung (2.7) uses chalocogenide technology characterized by the use of resistive heating of the material to change the resistive state of a cell. Hynix and Seoul National University (2.2) combine the features of Flash and DRAM, to produce DRAM characteristics during normal operations and non-volatile behavior at power-down. Motorola (2.3) uses an innovative cell architecture to achieve the highest MRAM capacity reported of 1 Mb and the fastest reported cycle time for MRAM of 130 ns. It uses a novel toggle magnetic tunnel junction technology that will easily integrate into a standard CMOS process. Virage Logic (2.4) will report a new reference voltage scheme for ferroelectric memories to provide improved reliable operation at voltages as low as 0.9 V.

Tuesday morning’s Session 11 on DRAM will introduce a low-power memory for extended battery life of handheld electronics. United Memories and Sony (11.1) employ an on-board macro to implement innovative transistor-biasing techniques, scaling the operating voltage to almost half of previously reported levels. Samsung (11.6) will describe a DDR-SDRAM graphics application that will translate into a more realistic video-gaming experience. The part utilizes a wave-pipelined control system to support a wide frequency operating range, from 300 to 800 MHz.

Wednesday afternoon’s Session 27 will feature an SRAM that achieves a breakthrough in low-power mobile operation. Hitachi, SuperH, and Renesas Technology (27.2) will report on an on-chip SRMA with a standby mode consuming only 30 microwatts, and an active power of 0.4 miliwatts at 300 MHz. Intel (27.3) will report a record-breaking cache on a microprocessor chip for server and CPU applications. It has a 54-Gb/s read-write bandwidth. At 533 million transistors, the SRAM cache uses 90% of the total number of transistors on a 432-mm2 chip.

Signal Processing
With only two sessions during ISSCC, the significant results in signal processing are a few fabulous consumer applications.

Real-time encoding of motion pictures has been limited to broadcast TV quality because of a lack of computation power. The potential high-definition (HD) compression standard (JPEG 2000) for recording, playback, and transmission of full-motion movies would require tens of billions of operations. During Wednesday morning’s Session 18, Sanyo (18.1) will describe the world’s first single-chip codec for real-time compression of full-motion movies and HDTV signals. It will enable Web-based movie distribution and real-time recording, such as HD digital cameras and surveillance applications.
With no fully integrated support for multimedia, Bluetooth, GPS, and modem on a current cellular baseband chip, the industry would enhance consumer multimedia experience with such a solution. Qualcomm (23.3) will present the first cellular baseband chip with fully integrated support for multimedia, Bluetooth, GPS, and modem on Wednesday afternoon. It is the highest level of integration published for cellular baseband chips.

Technology Directions
In Session 7 on Tuesday morning, Mark Horowitz of Stanford University will focus on how interconnect-centric tiled architectures can overcome wire delay limitations. Local communications schemes will replace global schemes to enable future technology scaling. Heterogeneous machines will have different modules tuned for specific applications.

The University of Twente (7.2) will introduce ways to circumvent the dramatic scaling of voltage and power consumption for analog circuits by exploiting available thin- and thick-oxide transistors. Special circuit techniques allow higher supply voltages to be used for analog than for digital circuits.

In Session 16 on Tuesday afternoon, Seiko-Epson (16.1) will present a cost-effective fabrication method for organic transistors using the inkjet printing technique. This paper illustrates the successful development and operation of an active-matrix backplane in applications such as smart clothing, plastic displays, and biomedical. The University of Tokyo (16.2) will present the use of plastic transistors for artificial skin. This flexible sensor can be used as artificial skin for robots. A simple cut-and-paste approach is proposed to customize the size of these circuits.

For more on the challenges and opportunities of organic transistors see Sodini and Bulovic's report on the Application-Driven Organic Electronics Workshop, page 8.
Session 24 on Wednesday afternoon will feature three extremely low-power, low-rate communication devices. The circuits must be optimized for low duty-cycle operation, and energy consumption is the primary design metric. A gas-chromatographer fabricated in less than a few cc by the University of Michigan (24.1) integrates digital compensation, self-test, and distributed power management on a wireless sensing platform. AnSem NV and Phonak Communications (24.2) will describe a very-low-power programmable FM receiver for hearing aids in less than 1 cc.

A flyspeck RFID by Infineon (24.3) is aimed at replacing barcodes. The small size and low cost (projected under one cent in large volume) of the chip is a direct consequence of a collection of cunning circuit innovations. It is powered directly from an interrogating RF supply without AC-to-DC conversion. Such AC operation of logic circuits eliminates the need for both rectification and filtering, providing considerable space savings. The RFID requires an on-product printed antenna loop.

Wednesday afternoon’s Session 24 will continue with a number of 60-GHz circuit devices, spurred in part by opening 7 GHz of a previously unlicensed bandwidth around 60GHz, and featuring aggressively scaled CMOS and Si Ge technologies.

Wireless Communications
Monday afternoon’s Session 5 will feature five papers from Spirea (5.2), New Logic (5.3), Atheros (5.5), IRF Semiconductor, and Stanford University (5.4) that describe transceivers for 802.11a/b/g. Each strives to reduce cost by using low-cost CMOS technology and architectures that minimize external components. Each implements transceivers for all three standards that will enable seamless universal connectivity. Atheros (5.50), Seoul National University, and GCT Semiconductor (5.6) will describe efficient generation of the LO signals, essential for WLAN. Developers from Universita di Pavia (5.7) will describe a receiver front end in SiGe that addresses performance issues. Researchers at the University of Tokyo (5.8) will describe a 4.3-GHz frequency divider that consumes just 44 microwatts, important for a mobile application.

During Tuesday morning’s Session 10, eight papers will feature radio on chips with varied integration levels, from an entire multi-mode GSM transmitter implemented in a 0.13-µm CMOS technology to an individual GSM power amplifier realized in a Si-LDMOS. A novel radio architecture presentation will explore the appropriate distribution of both the analog and digital blocks to realize the most efficient implementation from a performance and die-area perspective. Examples of digital and analog functions swapping traditional roles will be highlighted.

During Tuesday afternoon’s Session 15, two teams from TI (15.1 and 15.3) will describe cell phones and other small handheld devices that can exchange information over a short range, while using very little power and having ultra-long battery life. Sharp (15.6) will show that they also will be able to receive television signals, including new interactive services that combine the best of broadcast television with the interconnectedness of the internet, while maintaining very long battery lifetimes.

Wednesday morning’s Session 21 will focuse on silicon reaching for millimeter-wave frequencies. Today, we use a small fraction of the available radio spectrum. This is due to the limitations of existing radio architectures and semiconductor technologies. Ultra-wideband (UWB) systems (a new radio architecture) harness additional unused radio frequency bandwidth and increase data rates, but impose unusual demands on circuit design. TheCalifornia Institute of Technology (21.1) and Harvard University (21.2) will present creative ways to improve oscillator performance. University of Padova (21.3), Skyworks, and UCLA (21.4) will describe low-noise amplifiers for operation in the UWB band spanning 3.1 to 10 GHz. Silicon’s suitability for operation beyond 10 GHz will be well-demonstrated by several papers describing circuits with excellent performance at frequencies approaching 40 GHz.

Wireline Communications
Tuesday morning’s Session 9 will feature significant cost reductions in 10-Gb/s and SONET systems in highly integrated CMOS transceivers. These reports by Hitachi (9.1) and Aeluros (9.2) will mean faster, cheaper network connections to desktops and servers.

System integration and complexity create an ever-increasing need for I/O bandwidth. During Tuesday afternoon’s Session 13, a combination of faster process and new latch design from NEC (13.1) will achieve multiplexers at 120 Gb/s and demultiplexers at 110 Gb/s. Current standards had been limited to 40 Gb/s. IBM (13.3) will describe multiplexing with good jitter and lower power achieved at 108 Gb/s using half-rate clocking. These high-speed Mux and deMux chips enable the next generation of test equipment. The number of cables, connectors, and fibers can be minimized by sending data at the fastest possible serial data rates.

Helpful to telecom companies in competition with cable and satellite TV providers are practical lower-cost, lower-power, and higher-data rate ADSL2+ and VDSL. Described by Infineon (22.1) and TI (22.2) during Wednesday afternoon’s Session 22, these solutions will allow even high-quality video over twisted pair.

Wednesday afternoon’s Session 26 will feature many innovations for optical, and electrical-communication systems operating up to 40 Gb/s in silicon processes. They use on-chip electrical equalizers to extend the bandwidth of the integrated CMOS photodetector. The University of Twente (26.2), Netherlands, will describe a novel 3 Gb/s photodector that is about five times faster than previous designs. The University of California Irvine and Stanford University (26.7) will describe a novel detection of transition edge rate to provide adaptive equalization for copper cables between 1 and 5 meters at 10 Gb/s.