In February, the International Solid-State Circuits Conference 2000 (ISSCC 2000) showcased the outstanding new designs and ideas for faster, smaller, cooler, cheaper chips that advance the state-of-the-art and simplify the work of end product designers. In November and December, watch for the Journal of Solid-State Circuits, special issue which will publish journal-length papers of selected ISSCC presentations.
This year's analog papers spanned four sessions: Nyquist-Rate Data Converters, Filters and Amplifiers, Oversampling Converters, and General Analog techniques. Behzad Razavi, the ISSCC 2000 Analog Subcommittee Chair, re-ported that each session included record-breaking designs in CMOS and bipolar technologies.
In the first session, a 14-bit 100-MSample/s bipolar ADC and a 12-bit 65-MSample/s CMOS ADC are the fastest circuits reported to date for their respective resolutions. In the second session, a 10.7-MHz CMOS switched-capacitor filter is the first to achieve a well-defined, reproducible quality factor of 55, a critical feature for heterodyne RF receivers.
In the third analog session, two oversampling converters achieve an effective sampling rate of 2.5 MHz with a signal-to-noise ratio (SNR) of 90 dB and higher, providing low-cost solutions for DSL applications. A multibit converter providing 120 dB SNR is also reported. In the fourth session, a 6-bit 800-MSample/s ADC, targetting disk drive electronics, achieves the highest conversion rate at this resolution in CMOS technology.
CMOS designs continue to dominate research presented at the ISSCC 2000 because of its usefulness for wideband wireless communications and its key role in creating low-cost portable broadband communication devices.
Paper 8.1 reported the first DECT phone-on-a-chip. Digital self-calibration and offset cancelation techniques solved DC offset issues common in Zero-IF circuits. The chip includes a high level of digital processing within a radio transceiver operating at 1.9 GHz. The chip boasts complete integration except for the power amplifier and antenna switch.
A blinding 16.8 GHz in CMOS for a frequency divider was shown in Paper 12.1. This is a 3x speed improvement over previously reported 1.8-V CMOS dividers, while dissipating just 3 mW. The design used a new frequency divider topology that made use of mutually coupled flip-flops to achieve a low-cost device.
The industry's first complete analog front-end for HDSL2 was introduced at the conference. Digital Subscriber Line (DSL) technology offers a competitive alternative to broadband access for businesses and homes by using the installed base of twisted-pair telephone wiring. Although HDSL is the current choice for T1 replacement for business use, it is a proprietary standard that is currently hampering the interoperability of equipment from different vendors. Moreover, HDSL requires two copper pairs. Presently, HDSL2 overcomes these two problems by standardizing high-bit rate data delivery over a single copper pair at T1 speeds of 1.544 Mbps. This IC, [Paper 18.1], accommodates the extremely high dynamic range and peak-to-RMS requirement of HDSL2 created by the overlapped transmission of the upstream and downstream data.
Gigabit Internet backbone communications were described in two2 papers on SONET implementation. Paper 3.2 described a fully integrated receiver for SONET OC192 (10 Gb/s) contributing to higher -speed Internet service while achieving cost reduction. Another paper, 3.6, demonstrated clear progress towards integrated solutions with their chip-set for SONET OC768 (40 Gb/s).
Ian Young, Digital Subcommittee Chair, saw dramatic improvement in microprocessor performance this year over previous years, both in highest frequency clock rates reported and in the emergence of several brand-new microprocessor designs based on new architectural concepts. The 1- GHz barrier was crossed by no fewer than three microprocessors introduced at the conference. [Papers 5.1, 5.4, 5.7] Four of the microprocessors used the latest 0.18-µm technology that enables twice the number of devices per unit area, each operating faster and consuming less power per operation. [Papers 5.1, 5.2, 5.3, 5.7] Of those, one, a Ghz IA 32 Microprocessor [Paper 5.7] used aluminum interconnect to simplify the manufacturing pro-cess at the cost of added design complexity.
Two papers described the use of more than one type of n channel and p channel transistor threshold voltage on the same chip, allowing for the optimization of fast but hard to turn off transistors versus regular devices. In an IBM processor [Paper 5.6] and in an Hitachi processor [Paper 25.3], designers exploited the "lower-threshold" faster circuits in some systems on the chip, while still producing most transistors as the more controllable "higher-threshold" type. Paper 25.6 demonstrated use of a completely different method of modulating threshold voltage by dynamically adjusting the substrate bias to select speed and power.
New levels of chip integration were demonstrated in Papers 25.4 and 25.5, which include 17 and 4 independent processing units, respectively. Each of these on-chip processor units operates on its own instruction stream, greatly expanding the performance and flexibility of the chip. Similarly, to increase instruction-level parallelism in the traditional single-instruction stream processors, a doubling of transistors was used to increase the instruction per cycle. Paper 25.7 introduced the design of the much-anticipated IA 64 architecture, which makes use of Very-Long-Instruction Word (VLIW) concepts and advanced compiler technology to extract more performance from each instruction. The new SPARC processor presented in Papers 25.1 and 25.2 is able to execute up to seven instructions per clock versus four in the previous generation.
Self-adjusting clock distribution is a key technology for large gigahertz-class processors and digital ICs. Two papers present innovative approaches that minimize or eliminate the amount of interconnect required by using many DLLs or PLLs to locally generate the clocks needed in each region of the chip and to provide global synchronization. Paper 10.5 described an array of PLLs used in a distributed-clock network. Paper 10.6 described clock generation and distribution in the new IA-64 microprocessor.
Dennis L. Polla, subcommittee chair, highlighted new imaging techniques based on CMOS and CCD technologies. The CMOS contributions focused on innovative methods for reducing fixed-pattern noise (FPN), increased frame rate, and reduced power consumption. Paper 6.1 used a hole-accumulation-diode sensing approach to reduce FPN. Dark currents of 370 pA/cm2 were characterized at room temperature. Another FPN reduction technique in Paper 6.3 was implemented in the form of a 256 x 256-CMOS passive pixel imager with a differential architecture and correlated double-sampling output. This approach eliminated blooming effects often found in passive pixel approaches and demonstrated 0.1% pixel-to-pixel and 0.4% column-to-column FPN.
Paper 11.7 presented an embeddable low-power SIMD processor. The imager showed a new approach for future digital imaging system requirements of real-time image processing and real-time video compression. A prototype processor with 9.6-µm-pixel pitch was realized in a 0.6-µm, three-layer metal CMOS technology and showed 20-mW peak power consumption at 25 MHz and 2.5 V.
A variety of integrated sensors based on MEMS technologies were presented. A miniaturized ultrasound range finder microsystem based on thermally excited silicon membrane transducers and a standard 0.8-µm CMOS technology was presented in Paper 11.1.A single-chip wireless pressure sensor provided an excellent demonstration of MEMS wireless power and data transmission up to distances of 1 m in Paper 11.4.
T. S. Jung, the session chair on DRAM, reports that DRAM designers are exploring two avenues for increased performance: embedding portions of DRAM onto logic devices and using high-speed synchronous interface to stream data on and off stand-alone memory devices.
This year, designers of the embedded DRAMs, have optimized the cycle and access time to match the applications, employing pipelining to achieve clock speeds of up to 1 GHz and an access time <4 ns. [papers 24.1, 24.2, 24.3, 24.4]
For discrete DRAMs, higher frequencies and cost reduction are the focus. Area-efficient DLL and cancelation of system skews are employed to achieve optimal re-timing of received and transmitted data [Papers 24.6, 24.7]. Cost improvements are achieved, both by more efficient core organizations and use of packaged-part tuning techniques that allow more devices to meet the tighter I/O timing specifications required in high-bandwidth interfaces [Paper 24.8].
Steve Molloy and Bernard Shung selected these highlights from the signal processing sessions.
Reporting energy levels between 50 and 100 MIPS/mW, about eight times lower than conventional DSP processors, Paper 4.1 described a flexible implementation of baseband wireless functions integrated four programmable processing elements and a global resource controller connected to a high-performance split-transaction bus. This multiprocessor DSP chip achieves 1.6 billion 16-b MAC operations per second.
Paper 14.1 presented the first fully integrated audio/video/systems MPEG-4 simple profile codec. Three RISC processors and required memory are included in 117 mm2, implemented in 0.25-µm CMOS.
A complete IP phone solution from audio samples to TCP/IP packetized data was presented in Paper 14.4. The terminal processor integrates a 32-bit RISC CPU, two 10/100 Base-T MACs and 2 Mb of SRAM.
John Cressler, Chair of the Technology Directions Subcommittee, highlighted the following papers from sessions on low-temperature circuits and diagnostic techniques for microprocessors, emerging memory and device technologies, and high- frequency wireless.
Chip cooling will drive the next increment in microprocessor performance. 0.1-µm CMOS conventional and SOI digital circuits optimized for sub-ambient temperature operation can achieve as much as a 3.3% speed improvement per 10¡C decrease in temperature. Moreover, copper interconnect improves by 3.6% per 10°C decrease in temperature. Backside thin-film thermoelectric cooling will allow migration of sub-ambient operation from server applications to PCs [Papers 13.1, 13.2]
New optical diagnostic tools allow noninvasive debugging of critical paths and verification of timing models for microprocessors. Backside optical probes developed in Paper 13.4 have a spatial resolution approaching that of a single transistor and provide 50-ps resolution timing analysis of an operating 0.18-µm microprocessor. In paper 13.5 backside picosecond image circuit analysis identifies cycle-time-limiting conditions. This analysis was fed back to hardware simulation for model tuning and im-proved manufacturing models.
For breakthroughs in memory technology, MEMS technology may be the key for disk storage density, and magnetic-junction RAM may be the key for fast, low-power nonvolatile memory. Paper 7.1 reports on a very-large-scale nano-mecha-nical system that impresses data on the surface of a polymer, with a demonstrated density of 200 Gb/in2. Average read access-time is comparable to todayÕs hard disks, but at lower power levels. Papers 7.2 and 7.3 rely on arrays of magnetic tunnel junctions (MTJ), written by passing data-dependent currents through orthogonal conductors and read by discriminating between the different resistances induced by the low magnetic polarization states of the MTJs. The authors differed in their ap-proaches to sensing the two states, with an interesting trade-off between the area required to store a bit and circuit sensitivity to process variations. The high voltages required to write Flash memory are avoided.
Numbers in brackets refer to the paper numbers in the published proceedings of the conference. The Digest of the ISSCC is available as a soft-cover volume. The ISSCC 2000 CD-ROM version also contains the Slide Supplement which has the slides of each presentation as well as the Digest of Technical Papers on the 1999 Symposium on VLSI Circuits. Order online at the IEEE store: www.shop.ieee.org/store/. Key in ISSCC in the form blank on the Web page and click on the Search button. |