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Kerry Bernstein IBM Burlington, VT kbernste@us.ibm,com |
Process engineers have provided generation after generation of CMOS technologies that somehow continue to fulfill Moore's Law. Architects have shrewdly exploited this capability with innovative schemes that increase parallelism and pipeline depth, change instruction execution order, and drive more speculative operations. These techniques have improved architectural performance at the expense of power, die size, and complexity. Our panelists shared very polarized opinions on whether these boundary conditions and their trends were sustainable and remained practical or if alternative design paradigms are becoming apparent.
The Patterson-Hennessy Equation indicates the time required to complete a transaction may be enhanced by improving (1) the number of instructions the chip can retire per cycle, (2) the number of cycles required per instruction, or (3) the number of seconds the machine consumes per cycle. David Harris, Assistant Professor of Engineering at Harvey Mudd College, argued that because of diminishing returns in architecture performance, it was more profitable to spend resources on high-performance circuits rather than on increasing architectural overhead [item (3) above]. He also noted that increased exposure to noise and skew identified selected circuit topologies, such as skew-tolerant domino, as being "best fits" in future chips.
Kazuo Yano, Senior Researcher at Hitachi's Central Research Laboratory, countered that a mix of circuits styles, each well suited to a given function, will be found on successful microprocessors of the future. He added that each of these styles will also thrive with selected technology features to enable them.
Perhaps even more outspoken, but with a similar outlook, Bob Montoye, Research Staff Member at IBM's Austin Research Laboratory, described the circuit design "dark age" that aggressive architectures and technology worship have created. He argued for designing to the original simpler metrics of latency and bandwidth.
On the other end of the spectrum, Yale Patt, Professor of Electrical and Computer Engineering at the University of Texas, reminded the audience that the design community has indeed coped well with the complexity and device count that contemporary architectures have conjured up. Prof. Patt believes that the innovation and creativity bringing the industry to this point will continue to deliver solutions that manage complexity.
David Patterson, Pardee Professor of Computer Science at the University of California, Berkeley, encouraged the audience to look beyond the present paradigm in stand-alone processors. By paying close attention to predominant functions required, Prof. Patterson believes substantial underutilized capability exists in the embedded space and in the server market. Each, he argued, drives specific requirements, which when customized can produce superior throughput.
Ruby Lee, Hamrick Professor of Electrical Engineering at Princeton University, extended this concept of customizing compute resource to the task. Prof. Lee argued that programmable processors, scalable power and clock cycle, and dynamically reconfigurable machine instruction sets are critical to producing chips with performance and power characteristics well suited to a multiplicity of market applications.
Audience participation highlighted the industry awareness of the baggage carried by these complex architectures. Array multiprocessing, possibly using simpler, lower power microprocessors, will clearly be a relief to the design community, but it is gated by the development of applications and compilers that have figured out how to harness this computing capability via job partitioning.
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Kerry Bernstein IBM Burlington, VT kbernste@us.ibm,com |