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A 550 Mb/s Radix-4 Bit-Level Pipelined 16-State 0.25-um CMOS Viterbi Decoder. |
The Electrical Engineering and Computer Science (EECS) Department of RWTH Aachen, Germany, chaired by Prof. Dr. Tobias G. Noll, has three fundamental research domains: physical oriented VLSI design methodologies, VLSI architectures and circuits for digital signal processing, and digital signal processing in medical electronics.
An important outcome of the research on design methodologies is the prototype implementation of a data path generator (DPG) tool. Starting from a high-level description of the signal flow graph (SFG) to be implemented, this tool automatically assembles highly optimized hard macro layouts from a set of abutment cells. These abutment cells again are automatically derived from a small library of predesigned optimized leaf cells. This approach exploits the inherent regularity and locality typically associated with SFGs of digital signal processing for superior features in throughput rate, silicon area, and even more important, power dissipation. It offers the possibility of iterative optimization of the SFG by simply modifying the SFG description, it supports the implementation of parameterized generic SFGs for frequently used building blocks such as IP blocks, and it can also be applied as a generator that is simple to use in dedicated macro generation. The tool is not limited to arithmetic data paths, but also allows the implementation of highly efficient building blocks such as customized memory macros. It is integrated into an industrial standard design framework and combines the advantages and flexibility of physical oriented design with short design times comparable to today's synthesis-based high-performance designs. (For detailed information, see www.eecs.rwth-aachen.de/dpg/info.html .)
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A 550 Mb/s Radix-4 Bit-Level Pipelined 16-State 0.25-um CMOS Viterbi Decoder. |
Research highlights from the VLSI architectures and circuits activities demonstrate the strengths of physical oriented design: A Viterbi Decoder for hard disk read/write channel applications was designed for a symbol rate of 550 Msymbols/sec, consuming about 500 mW on less than 1 mm2 in a 0.25-µm CMOS technology. The overall design effort from scratch to the verified hard macro, characterized by all views required in the design framework, was as small as 3 man-months. For video broadcast applications, another Viterbi Decoder was implemented in a 0.35-µm CMOS technology. Operating at 90 MHz, the decoder's power dissipation of only 120 mW outshines other recently published realizations of the same specification in comparable technologies.
For application in handheld ultrasound scanners, a digital beamformer chip is currently being developed in cooperation with Pie Medical, Maastricht, The Netherlands and Fraunhofer Institute IMS, Duisburg, Germany. The cardinal goal of that design experiment, which is funded by the European Commission, is the lowest possible power consumption that allows long-time battery operation of the system.
A rather new activity targets for highly efficient reconfigurable heterogeneous architectures for challenging single-chip signal-processing systems. In cooperation with the industrial partner Sony, implementation cost models are elaborated that support the partitioning of such systems. The implementation alternatives considered include DSP kernels, reconfigurable (FPGA-like) arrays, and dedicated macro blocks. Such heterogeneous architectures will be required in the future to fulfill the many-fold requirements of future Systems-On-A-Chip; for example, for flexibility (i.e., programmability and/or reconfigurability) for the highest computational power with a small silicon area and especially for power dissipation.
Concerning international studies at RWTH Aachen, the EECS Department of the Aachen Institute of Technology is coordinating a master's degree program in computer engineering for students from foreign countries already holding a bachelor's degree. Therefore, the EECS Department is interested in obtaining information about the research focus of academic institutions of other SSCS chapters in Europe, especially in Eastern Europe and countries of the former Soviet Union. Cooperative research and the establishment of cooperation for student exchange are most welcome here.