Background
To say that 1975 was a period of change for analog integrated circuits would be an understatement. For all that happened then and all that followed in the industry, I have felt lucky to be involved. However, the project came about not as the result of luck but as the first leg of well-guided strategy by several professors at the University of California, Berkeley (UCB), to make "MOS analog" a reality. In particular the guidance that I received from Professors Paul Gray and Dave Hodges was invaluable to the success of the project. I will always be indebted to them. Looking back, the concept of the paper seems obvious today, but at the time this was uncharted territory full of unknowns and the fear that if feasibility could not be demonstrated, I would be a graduate student forever.
During that period analog products were dominated by bipolar technology with laser-trimmed thin-film resistors for quantizing current-a mature, accurate, and dominant technology. However, this was not cost-effective for products requiring large digital circuits. In contrast, MOS technology provided high-density, low-cost digital circuits but relatively mediocre 8-bit accurate analog circuits. The strategy at Berkeley was to eliminate this barrier starting with new techniques for MOS data converters. Fortunately, I was able to be a part of this effort.

The Data Converter Challenge
The feasibility of creating MOS current sources that could compete with bipolar was discarded from the beginning and a new approach of working with charge was considered to be more attractive. Working with charge was intriguing because the high impedance of the MOS gate would hold charge with minimal loss. Precision charge quantizers needed for data conversion had not been developed and the viability of such a technique required overcoming a variety of perils including: dielectric absorption, temperature coefficient, voltage coefficient, parasitic capacitance, switch feed-through, and matching requirements.

The Charge-Redistribution A/D Converter Project
A novel circuit was developed and fabricated in the UCB semiconductor lab in NMOS technology. The particular test chip was a 10-bit quantizer and comparator that comprised the key blocks of a 10-bit A/D converter. Numerous problems were encountered that resulted in a redesign of the capacitor array to improve matching. Process and instrumentation improvements provided data that led to identification of the sources of error and what would be required to further reduce these. Ten-bit accuracy was achieved.

ISSCC Presentation and JSSC Paper
The project was presented at the 1975 ISSCC conference and was voted one of the "Best Papers" of the conference. Because of this, Professor Gray (now Vice Chancellor and Provost at UCB) was relentless in the pursuit of perfection for our December 1975 JSSC paper since he believed that it "might be heavily referenced." The paper was especially important because many of our peers were skeptical about the viability of charge-redistribution even after the conference paper. Over the following two months, the paper was revised and revised without mercy. During this process significant additional lab work was performed and more precise data was taken that allowed identification and measurement of error sources as well as detailed suggestions for reducing error sources. As a result, the paper reflected a heavy emphasis upon teaching others how to implement the new technique. It included a full disclosure of what was done in the design of the circuit and how to reduce the remaining error sources. Supporting data was provided and anticipated questions were answered proactively. This was essential to convey the reality of charge-redistribution to a skeptical peer group. The paper became the perfect template for others to use to replicate the technique. This is exactly what happened over the next few years. As co-workers were able to reproduce and improve upon the results, skeptics became believers, ideas became reality, and the market began to see a new generation of MOS data converter products based upon charge-redistribution.

Industry Impact
The essence of the novel circuit was that it inherently included a sample-hold circuit, and the sample-hold capacitor was the same capacitor used for the quantizer. This reduced area by a factor of two and eliminated the need for an external sample-hold circuit. Also intrinsic in the design was the elimination of the parasitic capacitance by creating a virtual ground at the capacitor top plate and the driving of the bottom plate by voltage sources. This allowed high accuracy in the technique independent of the parasitic capacitance. In addition the technique of charge-redistribution requires zero DC current-making it suitable for low-power applications. All of these benefits provided a cost-performance tradeoff that exceeded conventional technology at the time. This led to a fundamental patent. Within the next two years charge-redistribution was used in PCM CODECs and switched capacitor filters used in telephony. Within the next five years this technique became the dominant approach for digital telephony throughout the world and was licensed by nearly all major telecommunications companies during the seventeen-year lifetime of the patent.

Legacy
The legacy of the work done at Berkeley in 1975 was more fundamental than its impact upon telephony. Moreover, the work published in the JSCC paper demonstrated that while bipolar technology provides excellent current quantization, MOS technology provides superior charge quantization. In order to implement mixed analog-digital ICs that required high accuracy, it was necessary for analog designers was to think in terms of charge rather than current-quite a challenge for 1975. The technique is described in most CMOS analog IC design textbooks used in the classroom today.

Jim McCreary
Xicor, Inc.
jmccreary@xicor.com