by Stewart Taylor, Program Chair
As a service to Solid-State Circuit Society members, the ISSCC99 program subcommittee chairs and several of their subcommittee members have selected and commented on some of the significant papers presented at the 1999 ISSCC in each of their respective disciplines. We hope you find it interesting.
Paper #18.6, "A 6b 500MS/s CMOS Flash ADC with a Background Interpolated Auto-Zeroing Technique," by K. Yoon et al. of Seoul National University, presented a circuit that achieves a high sampling rate in a 0.6-mm technology through the use of offset cancellation rather than large transistor dimensions. Paper #23.1, "A 450kHz CMOS Gm-C Bandpass Filter with +/-0.5% Center Frequency Accuracy for On-Chip PDC IF Receivers," by H. Yamazaki et al. of Fujitsu, described a bandpass filter tuning technique based on the natural frequency of the filter in response to a step input. The accuracy achieved using this method is one order of magnitude higher than that of other techniques. Finally, paper #23.3, "A 2.5 Gb/s Adaptive Cable Equalizer," by M. Shakiba of Gennum Corporation, presented the fastest equalizer built in silicon technology. With 100 meters of cable, the circuit provides an open eye with a peak-to-peak jitter of 80 ps.
Did you miss a "hot" presentation during the busy 1999 ISSCC schedule? The accompanying retrospective comments on some of the significant selections. See the November and December issues of the JSSC for journal length papers of selected presentations.
Paper #11.2, "A 500MHz 1.5MB Cache with On-Chip CPU," by J. Lachman, et al. of Hewlett Packard, described three 0.5MB embedded SRAM arrays that achieve 16GB/s aggregate bandwidth with 2ns cycle time and latency. Paper #11.6, "An 18Mb, 12.3GB/s CMOS Pipeline-Burst Cache SRAM with 1.54Gb/s/pin," by C. Zhao, et al. of Intel, presented a very large SRAM with 770MHz DDR on 64 pins. SRAM was challenged by DRAM with a combination of speed and size in paper #24.4, "64Mb 6.8ns Random Row Access DRAM Macro for ASICs," by T. Kimura, et al. of NEC. Paper #6.6, "A 130mm2 256Mb NAND Flash with Shallow Trench Isolation Technology," by K. Imamiya, et al. of Toshiba, described the smallest 256Mb flash die using 0.25mm STI Technology. Additionally, it achieved a fast program time of 200ms/ 1Kbyte(one page). Finally, paper #24.7, "A 390mm 16-bank 1Gb DDR SDRAM with Hybrid Bitline Architecture," by T. Kirihata, et al. of IBM, demonstrated an array efficiency of 67% and 1.6 GB/s data rate.
Achieving a fast program time of 200 ms/1Kbyte, Imamiya described the smallest 256 Mb NAND flash die using 0.25mm STI technology.
Paper #19.1, "A Single-Chip Universal Digital Satellite Receiver with 480MHz IF Input," by A. Kwentus et al. of Broadcom, presented significant achievements in the level of mixed-signal integration. This 1.2M transistor, 0.35mm CMOS chip contains two 8-b A/Ds operating at 128MHz sample rate on the same substrate as a digital BPSK/QPSK/OQPSK receiver, Viterbi decoder and Reed-Solomon decoder. Paper #19.2, "A Single-Chip Universal Cable Set-Top Box/Modem Transceiver," by L. J. DŐLuna et al. of Broadcom, described a milestone in the integration of cable modem components. It is the first reported chip that incorporates both the burst-rate upstream modulator together with two downstream demodulators (1 for TV and 1 for access control). Paper #2.5, "260 Mb/s Mixed-Signal Single-Chip Integrated System Electronics for Magnetic Hard Disk Drives," by S. Nemazie et al. of Cirrus Logic, presented the first IC that integrates the four major VLSI functions required in magnetic hard disk drive systems. This CMOS IC contains a read channel, an ATA hard disk controller, a micro-controller (with an ARM RISC mP, ROM, and RAM), and a motion-control servo block. Paper #2.4, "360Mb/s (400MHz) 1.1W 0.35mm CMOS PRML Read Channels with 6 Burst 8-20x Oversampling Digital Servo," by S. Sutardja of Marvell Semiconductor, presented a CMOS IC that targets high capacity, low-power disk drives and achieves a 360 Mb/s channel rate in an industry-standard 0.35 um digital CMOS process. Paper #14.1, "A 0.5mm CMOS ADSL Analog Front-End IC," by J. Cornil et al. of Alcatel Bell, and paper #14.2, "A CMOS Analog Front-End IC for DMT," by C. Conroy et.al of DataPath Systems, described high performance analog front ends for DMT-based (Discrete Multi-tone) ADSL systems, operating with full data rate (1.5MB/s) over 18kft phone lines. Paper #14.7, "A 52Mb/s Universal DSL Transceiver IC," by R. Joshi et al. of Broadcom, described a fully integrated QAM-based VDSL system with up to 52Mb/s data rate. Paper #15.1, "A Microprocessor with 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and MPEG2 Decoder," by K. Kutaragi et al. of Sony, described a highly integrated system with multiple processing units suitable for the hand-held game market. This complex chip contains a MIPS-compatible CPU and two floating-point vector units, an image processing unit, and 10-channel direct memory access controller. Paper #15.3, "A 2.5GFLOPS 6.5 Million Polygons per Second 4-Way VLIW Geometry Processor with SIMD Instructions and a Software Bypass Mechanism," by N. Higaki et al. of Fujitsu, described a high-performance graphics processor with all bus unit interfaces on-chip for seamless integration into PC systems.
A milestone in the integration of cable modem components for set-top boxes, D'Luna et al. reported the first chip to incorporate both the burst-rate upstream modulator together with two downstream demodulators.
Papers #25.3 and #25.7 by M. Canada et al,. and D. Allen et al., of IBM, presented the first functional processors in partially depleted SOI technology resulting in a 20% improvement in clock frequency. Solutions to SOI circuit design issues were also discussed for the first time. Paper #5.1, "A 500MHz 64b RISC CPU with 1.5MB On-chip Cache," by P. Barnes of Hewlett Packard, describes a processor with over 100 million transistors in a 0.25mm process (75% are in the large L1 cache) with the highest reported performances at SPECint95 of 30 and SPECfp95 of 50. Paper #5.4, "A 7th Generation x86 Microprocessor," by S. Hesley et al. of AMD, presented a completely new architecture supporting 3 instructions per cycle to independent integer and floating point schedulers with advanced high-speed logic circuits that allow operation above 500MHz. Paper #5.7, "A 600Mz IA-32 Microprocessor with Enhanced Data Streaming for Graphics and Video," by S. Fisher et al. of Intel, described a next generation P6 processor with up to 650MHz operation, 70 new IA-32 instructions, and 8 new 128b registers, implemented in a 0.25mm process.
Order the 1999 ISSCC Digest for $125 or CD-ROM for $75 through Prof. John Wuorinen, 2 School St., Castine, ME 04421-0304. FAX: 207-326-8878. Questions or for availability of previous year's materials, please contact Prof. Wuorinen at 71762.2626@compuserve.com.
Paper #22.4, "A 60dB Gain 55dB Dynamic Range 10Gb/s Broadband SiGe HBT Limiting Amplifier," by Y. Greshishchev et al. of Northern Telecom, described a limiting amplifier in SiGe HBT technology for low-cost 10Gb/s fiber-optic applications with a sensitivity of 3.5mVpp, >60dB gain, and AM to PM conversion <5ps. Paper #22.6, "15mW 155Mb/s CMOS Burst-Mode Laser Driver with Automatic Power Control and End-of-life Detection," by E. Sackinger et al. of Lucent Technologies, presented a burst-mode laser driver for the customer-end of an ATM-based passive optical network (PON). This 155Mb/s, low-power, laser driver automatically adjusts the current in the laser to maintain constant (+/-5%) output power over temperature, data patterns, and power supply variations. Paper #9.5, "A 622Mb/s 256k ATM Resource-Management Circuit," by Phillippe Gallay et al. of France Telecom, described a circuit architecture for a traffic and control algorithm needed to resolve conflicts from multiple connections arriving at the switch. Paper #13.1, "A Wide-Band Direct Conversion Receiver for WCDMA Applications," by Parssinen et al. of the University of Helsinki, presents the first prototype chipset for a direct conversion receiver that uses wideband code-division multiple access (WCDMA) at 2GHz. The front-end noise figure is 5.3dB while the image-reject downconverter has a very high IIP2 (+60dBm), as required for direct conversion.
Nemazie et al. described the first CMOS IC that integrates the four major VLSI functions required in magnetic hard disk drive systems; a read channel, an ATA hard disk controller, a microcontroller and a motion-control servo block.
Paper #7.6, "A CMOS Micro Touch Pointer," by N. Manaresi et al. of the University of Bologna, presented a new idea for miniature track ball pointing devices for portable applications such as palmtop and credit-card size computers. Paper #7.7, "A 100 Frame/s CMOS Active Pixel Sensor for 3D-Gesture Recognition System," by H. Miura et al. of Toshiba, described a new technique to analyze the complicated 3D motion of an object by a PC in real time. Multiple technologies of CMOS image sensors and real-time signal processing methods produced a compact system capable of human/object gesture recognition at 100 Frame/s. Paper #17.3, "An Integrated 800x600 CMOS imaging System," by W. Yang et al. of Hyundai, presented a high resolution CMOS imager derived from a DRAM process rather than a conventional logic processes. The result is enabling additional imaging functions including data buffering, data correction, and increased flexibility through programmability.
SiGe has moved from R&D into commercial applications as reported by both Subbanna et al. and Bopp et al.
A 20% improvement in clock frequency by using partially depleted SOI technology for functional processors was described for the first time along with new solutions to SOI circuit design issues in papers by Canada et al. and Allen et al.
Paper #4.1, "How SiGe Evolved into a Manufacturable Semiconductor Production Process," by S. Subbanna et al. of IBM, and paper #4.2, "A DECT Transceiver Chip Set Using SiGe Technology, " by M. Bopp et al. of TEMIC showed that SiGe has moved from R&D into commercial applications. Paper #4.5, "High Frequency Analog Filters in Deep-Submicron CMOS Technology," by R. Castello et al., and paper #4.6, "Analog Broadband Communication Circuits in Pure Digital Deep-Sub-Micron CMOS," by K. Bult of Broadcom, demonstrated that analog communications circuits can be built in pure digital deep-sub-micron processes. Finally, paper #12.6, "A Wireless Single-Chip Telemetry-Powered Neural-Stimulation System," by J. Von Arx et al. of the University of Michigan, described a circuit using the RF field for both power and data transmission, allowing an implantable device to remain permanently implanted without the need for batteries or external wires.
Monday - Wednesday
February 7 - 9, 2000
San Francisco Marriott Hotel, San Francisco, Ca
Authors should submit 3 items for review. A draft of the final manuscript for the Digest of Technical Papers and an abstract to be used in the Advance Program are required. Abstracts of accepted papers will be disclosed to the press at ISSCC Press Conferences that occur in early November. Additional supplementary material is not mandatory but strongly encouraged. Authors must clearly indicate a single subject area under which their paper should be reviewed. For the complete list of topics, see the full call for papers on the conference web site.
ISSCC is the premier global forum for debut of technical innovation in such areas as architecture, circuitry, and algorithms. The Conference pre-publication policy intends to maintain that. Yet contrary to popular opinion, a paper may be acceptable even if it is connected with a product that has sampled, entered production, and/or appeared in a publication. See more details and submission advice on the conference web page. The Program Committee will be the final judge.
45 copies of each submission must be received in Washington, DC: Friday, September 10, 1999. Additional copies may be required depending on an authors' geographical origin. Use of express delivery service is required for traceablity. Papers received after the deadline will be returned to authors unopened.
Limited financial assistance is available to student presenters upon request.
There are many more details of author instructions and an author's check list on the Conference Website: http://www.isscc.org. Be sure to review the complete submission requirements!