The European Solid State Circuits Conference ESSCIRC ‘98 was held in The Hague, The Netherlands, September 22-24, 1998. The program was divided into four themes: Communication, Analog and ADC, Digital and Signal Processing, and Sensor Interfaces. In retrospect, the most significant papers from the above areas will be briefly mentioned.
A strong interest in work on communications is reflected in the following papers. A 1W 1.9GHz CMOS class E power amplifier for wireless communications was presented in paper 1.3.1 by K.C. Tsai and P.R. Gray. At 1 W a 48% Power Added Efficiency was obtained with a 2V supply. In this field CMOS shows an incredible performance. Paper 1.3.3 by T. Yamawaki et al., described a dual band transceiver for GSM and DCS1800 applications. The 14.4 mm2 device fabricated in a 0.6 mm technology meets GSM and DCS1800 specifications. A 0.25 mm CMOS I/Q-channel down conversion mixer with active coil for DCS 1800 applications was presented in paper 1.1.1 by J. Janssens et al. At an LO of -9 dBm, a conversion gain of 24.8 dB, a noise figure of 21.5 dB and an IIP3 of 21 VdBm is obtained. Paper 1.2.1 by M. Borremans and M. Steyaert, described a high-speed, direct up-conversion transmitter for cable applications using very linear 0.5 mm "cold" CMOS mixers. A single-ended 1.5 GHz 8/9 dual-modulus prescaler in 0.7 mm CMOS with low phase noise and high input sensitivity was presented in paper 3.3.1 by B. De Muer and M. Steyaert. At 1.5 GHz, powered from a 5 V supply, it consumes 55 mW with a phase noise as low as -112 dBc/Hz at 1 kHz offset. Paper 3.3.3 by W.T. Bax et al., described a GSM demodulator based on a delta-sigma frequency discriminator with improved input sensitivity. Realized in a 0.8 mm BiCMOS technology, the system consumes 75 mW at 3 V supply and needs 9 mm2 die area. Paper 3.9.3 "Design of spiral inductors on silicon substrates with a fast simulator" by L. Lee et al., discussed a simulator that analytically solves the electromagnetics associated with spiral inductors and accurately models all important parasitics.
Four interesting techniques were presented to improve the quality of integrated oscillators. Paper 1.4.1 "Resonance-mode selection and crosstalk elimination using resonator-synchronized relaxation oscillators" by J.R. Westra et al., used relaxation oscillators to solve the problem of mode selection in multi-mode resonators. Paper 1.4.3 "A coupled sawtooth oscillator combining low jitter and high control linearity" by S.L.J. Gierkink and A.J.M. van Fuyl, showed a simple and effective way to reduce noise in relaxation oscillators. Paper 3.4.1 "A universal 0.03 mm2 one pin crystal oscillator in CMOS" by J.A.T.M. van den Homberg, showed a flexible crystal oscillator circuit with integrated load capacitor. Paper 3.4.2 "Reduction of intrinsic 1/f device noise in a CMOS ring oscillator" by S.L.J. Gierkink, et al., explored 1/f noise intrinsic quantitatively and showed how a reduction of 8 dB can be obtained.
Two creative amplifier techniques were presented. Paper 3.6.1 "A power efficient audio amplifier combining switching and linear techniques" by R.A.R. van der Zee and A.J.M. van Tuyl, presented a class-D power amplifier with a reduced external filter due to a class-AB correction amplifier. Paper 3.6.2 "A low power, low noise, variable gain amplifier" by C.H.J. Mensink, combined variable transconductance with shunting to obtain a THD of less than -66 dB in a dynamic range of 68 dB.
This year’s ADC papers show interesting advances in circuit design. A multi-bit sigma-delta modulator in floating body silicon-on-sapphire CMOS technology for extreme radiation environments shows 9.7 bits of dynamic range over a 63 kHz bandwidth. After 23 Mrad(Si) radiation, the resolution reduces to 9.1 bits, as reported in paper 3.2.1 by C.F. Edwards et al. A 500 Ms/s 6-bit Nyquist rate ADC for disk drive read channel applications having an ENOBs of 5 bits at 200 MHz analog input was reported in paper 3.1.1 by I. Mehr and D. Dalton. A 40 MHz CMOS sample hold, operating at 1.2 V was presented in paper 3.2.2 by A. Baschirotto. At 600 microW power, the double-sampled S/H achieves a THD better than -50 dB with a 2 MHz input signal and a 40 MHz sampling clock. In paper 2.2.1, D.B. Kasha, et al., presented a fourth order sigma-delta converter using only 16 mW and achieving a 122 dB of dynamic range over a 400 Hz bandwidth. A 3.3 V 15-bit delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications is presented in paper 2.2.3 by Y. Geerts. The converter uses a 2-2-1 cascade topology and achieves a SINAD of 82 dB with a 52.8 MHz sampling frequency. Power dissipation is 200 mW at 3.3 V supply. Paper 2.1.2 by J. van Engelen and R. van de Plassche, presented a fourth order bandpass sigma-delta modulator for 10.7 MHz IF conversion using a combination of LC and gmC stages. An IM3 of -76 dB is reached with 9 kHz signal separation.
A relatively large percentage of the contributions on digital processors came from the USA and Japan, while several contributions dedicated to multi-media and telecommunication applications originated from Europe. Techniques for enhancement of performance are pipelining and parallel architectures. Paper 1.8.1, "A 600 MHz Superscalar Floating Point Processor" by M. Matson et al. from Digital Equipment Corporation, described pipelining for several sections in the floating point unit of an out-of-order superscalar Alpha RISC processor. It implements IEEE and VAX data formats and is fabricated in a 2.2 V, 0.35 mm CMOS process. Paper 2.5.1, "Low Cost On-Die CMOS Distributed Voltage Regulation for Microcontrollers" by R. Nair et al. presented a low cost CMOS solution for on-die regulation of the power delivery. The design has a distributed architecture and the authors claim portability for future lower voltage processes with minor circuit modifications.
An advanced 0.21 mm CMOS low voltage process with 4 nm gate-oxide thickness has been used for the implementation of a reliable IO buffer. This design was described in paper 1.7.3, "A high Speed 3.3V IO Buffer with 1.9V Tolerant CMOS Process" by G. Singh. A design exercise on a 3D design in SOI on SOI technology was presented in paper 2.5.3, entitled "Low Power SOI CMOS Multipliers: 2D vs 3D", by Abou-Samra et al.. In this work, that is supported by the ESPRIT project HIPERLOGIC, the MOS transistors are situated in two SOI epitaxial layers, grown on top of each other by lateral overgrowth. This seeding technique provides large monocrystalline grain sizes. The p-channel transistors are implemented in the lower n-doped layer, while the n-channel transistors are in the upper p-type layer. In this way 3D designs are possible, which can considerably reduce interconnect length and hence the energy-delay product. Simulated performances of 2D and 3D designs of multiplier circuits are compared.
Four papers on various types of optical sensing were of particular interest. Paper 2.7.1 "A smart range image sensor" by M. de Bakker et al., discussed a sensor designed for sheet of light range imaging, using a smart PSD. Paper 2.8.1, "Integrated readout electronics for geiger-mode avalanche photodiodes" by W.J. Kindt and K.J. de Langen, opens the way to design picture images on the basis of photon count levels. Paper 3.7.2 "Analog VLSI implementation of early vision edge detection with noise suppression and image segmentation" by C.H. Yi et al., used an analog multiplexed two-layer parallel resistive network for Gausian filtering and image segmentation, and a new zero-crossing method for edge detection. Paper 3.8.3, "A high frame rate image sensor in standard CMOS technology" by N. Stevanovic et al., described a test chip with 128x128 active sensor cells equipped with an electronic shutter capable of acquiring 1030 frames per second. Paper 3.9.2 "A low-power and high-performance CMOS fingerprint sensing and encoding architecture" by S. Jung et al., described a sensor that acquires a binary fingerprint image that performs several image processing algorithms, including thinning the ridges of the fingerprint structure and extracting its characteristic features. A demonstrator chip with a 25x30 pixel array was shown.
Johan H. Huijsing
ESSCIRC '98
Technical Chair Program
J.H.Huijsing@ITS.TUDelft.nl