Sunny Orlando, Florida was the site of this year's Custom Integrated Circuits Conference (CICC), held 21-24 May. Conference highlights included a quartet of educational sessions, 129 technical paper presentations organized into 21 sessions (this year, for the first time, all technical authors presented their papers in PowerPoint format), spirited panel discussions, as well as an exhibit hall packed with leading companies from the semiconductor industry. Citing such factors as technical content, keynote and luncheon speakers, and location and convention facilities, this year's attendees rated CICC 2000 as one of the best ever!
The four educational sessions were: Current Issues in IC Design, System On A Chip, Broadband Communications, and Wireless IC Design. Each of the sessions contained four 2-hour tracks, providing attendees the opportunity to gain insight into new and/or emerging technologies or to brush up on existing skills.
Some of the key tutorials were an "Overview of circuit simulation techniques," "Design of high-speed D/A converters," "Design considerations for wireless SOCs," "Design issues and techniques for SOI circuits," "Modem fundamentals," "ADSL architecture," "RF system design," and "Phase-locked loops."
This year's keynote presentation was given by Joe Pumo, Director of SOC Design Technology Group, Motorola, and was entitled "SOC: The convergence point for solutions of the 21st century." His presentation focused on the challenge of delivering a complete solution that meets the customer's system re-quirements-function, performance, and price-in a competitive time-to-market.
Mr. Pumo discussed how SOC defines a product that is targeted for a specific application, which contains an entire system, including embedded software, as well as defining a process from developing the system specification through final product qualification (see Figure 1). Mr. Pumo's complete slide presentation can be downloaded from the CICC Web site: www.ieee-cicc.org/conference/keynote.
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Figure 1: Joe Pumo's keynote presentation on "SOC: The convergence point for solutions of the 21st century" is available online at www.ieee-cicc.org/conference/keynote . |
One of the most exciting presentations this year was given by Dr. Rudolf Danner of NASA's Jet Propulsion Laboratory. His talk, entitled "Of hummingbirds and undiscovered worlds: Optical interferometry and NASA's quest for habitable planets," discussed how NASA plans to use optical interferometry to find and characterize Earth-size planets orbiting stars other than our own Sun. Using this technique, scientists can determine if a planet contains the basic ingredients that they believe to be essential to support life, that is, (1) surrounded by an atmosphere at room temperature containing ozone and nitrogen and (2) evidence of liquid surface water. Dr. Danner's complete slide presentation can be downloaded from the CICC Web site: www.ieee-cicc.org/2000/conference/events/luncheon.html.
Historically, the CICC technical program has focused on nearly all aspects of integrated circuits, from fabrication to complete functional systems. This year was no exception, with sessions on process technology, test and reliability, custom and low-power circuits, embedded memory, analog design, wired and wireless communications, digital signal processing, programmable devices, Systems On A Chip (SOC) design and design methodologies. Nearly 300 technical papers were submitted, from which the program's 129 were selected. Several of the most noteworthy are discussed below.
"CMOS in the new millennium," an invited paper from T. Ning of IBM, addressed the challenges faced by CMOS technology as it approaches its ultimate scaling limits. The paper theorizes a limit of 25 nm for channel length, a gate oxide thickness of 1.5 nm, and a power supply voltage of 1 V, and then articulates the challenges of fabricating such a technology. Along the same lines of technology scaling, another invited paper, "Effects of technology scaling on digital CMOS logic styles," from M. W. Allam et al. of the University of Waterloo, Ontario, discusses the behavior of various logic circuit families for future technology generations, while predicting the effects of scaling on performance, hot carriers, leakage currents, and interconnects. In his paper, "A new design for complete on-chip ESD protection," A. Z. Wang of the Illinois Institute of Technology discusses a novel way of protecting against electrostatic discharge. His approach is compact, provides protection in all directions, is ultrafast with programmable threshold voltages, and its small size reduces parasitic effects, making it ideal for RF applications.
A high-resolution, low-voltage delta-sigma modulator analog-to-digital converter was presented by R. Naiknaware et al. of Washington State University, Pullman, in the paper entitled "142 dB DS ADC with a 100nV LSB in a 3V CMOS process." It achieves 142 dB dynamic range in a 100 Hz bandwidth and 132 dB dynamic range in a 1000 Hz bandwidth, while achieving roughly the same noise power density as a 1 kW resistor. The converter, suitable for high-performance instrumentation applications, uses correlated double sampling to reduce flicker noise contributions as well as a number of power optimization techniques enabling a total power dissipation of 22.8 mW from a 3 V supply. Another key analog paper, "A 2.5Gb/s clock recovery circuit for NRZ data in 0.4µ technology," by S. Butala and B. Razavi of UCLA, described a 2.5 Gb/s phase-locked clock recovery circuit utilizing a two-stage ring oscillator and sample-and-hold phase detector. To guarantee oscillations, each of the two stages has a load made of a transistor and an RC network that provides excess phase shift. Experimental results of the circuit presented show a recovered clock that has a RMS jitter of 10.8 ps.
In wireless designs, one of the critical steps in the drive for higher integration and lower system cost is the integration of traditionally external components. In the paper from F. Huang and Kenneth O of the University of Florida, Gainesville, "A 900MHz T/R switch with a 0.8dB insertion loss implemented in a 0.5m CMOS process," a novel single-pole double-throw CMOS T/R switch for 3 V applications is proposed. The 0.8 dB insertion loss is achieved by optimizing the transistor widths and bias points and by minimizing the substrate resistance. The input and output nodes are DC biased to achieve a high 1 dB compression point. A key issue for a T/R switch is withstanding the potentially large RF input voltage in combination with an output impedance mismatch. The worst case of an open load (total reflection of the input signal) is used to calculate the maximum power the switch can deliver while avoiding gate oxide breakdown. The CMOS oxide breakdown limits the maximum transmit power of this switch to 10 dBm into a 50 ½ load. Although the insertion loss of this switch is higher than discrete solutions used in today's cellular phones are, it could provide a cost-effective solution for ISM-band applications through integration with other CMOS components.
In the Embedded Memory session, a paper by P. Diodato et al. of Lucent, "Embedded DRAM: An element and circuit evaluation," de-monstrates the use of an advanced capacitor dielectric, Tantalum Pentoxide, in a novel embedded DRAM cell structure. This cell structure uses the Metal 1/Metal 2 Tungsten via as the bottom plate of the capacitor and Metal 2 as the top plate, forming what Lucent calls a MOM (Metal-Oxide-Metal) DRAM cell.
"A full accuracy MPEG1 Audio Layer 3 (MP3) decoder with internal data converters," by S. Hong et al. of Dongguk University, Seoul, Korea, describes a complete implementation of a full-accuracy MPEG1 Audio Layer-3 (MP3) decoder having on-chip ADC and DAC circuitry. A recycling-type ADC with sample-and-hold that greatly reduces power consumption was employed. A novel 32-bit floating-point DSP core was used, along with an efficient power management technique.
Finally, in the area of System On A Chip, the paper "Wire planning for performance and yield enhancement," by C. Ouyang et al. of Level One Communications, proposes a wire planning strategy at the layout stage that addresses the deep submicron issues facing both design and manufacturing engineers. In design, wire density affects system performance, while in manufacturing, wire density affects yield. From his experiment, the author has calculated the "sweet spot" for metal pitch, which results in optimal performance and yield. His conclusion points to the importance of wire planning and the unfinished business of incorporating such planning into commercially available placement and routing tools. In their paper entitled "Secure contactless smartcard ASIC with DPA protection," P. Rakers et al. of Motorola describe an SOC composed of RF circuits, receivers, bandgaps, embedded EEPROM, 8-bit microcontroller, and a noise isolation circuit realized in a 0.6 µm CMOS process. The result is a single-chip solution for contactless smartcard applications with a 2000 times reduction in digital signature amplitude to greatly increase security against DPA attacks. In addition to electrical and system-level-design problems, data security and encryption issues are covered. Finally, the IC operates without direct electrical or power connection, and I/O signals and power supply are obtained through RF connections.
The IEEE Journal of Solid State Circuits will devote its March 2001 issue to selected papers from CICC 2000. In addition, the full conference proceedings for CICC 2000 is available from the IEEE, +1 800 678 4333 (in U.S. and Canada), and +1 732 981 0060 (worldwide), catalog number CH37044-TBR. Visit the CICC Web site at: www.ieee-cicc.org/. Better yet, plan to attend CICC 2001 in San Diego, 6-9 May 2001!
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Jeffery H. Oppold
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