A panel of experts gathered in San Francisco in February to ask, can 100 million transistors in a 100-square-millimeter die be designed in 100 days? And the answer was . . . maybe. The good news is that the notorious productivity gap is being closed by re-use and platform-based design, but only for digital and memory-intensive circuits, as industry is increasingly looking to integrate and re-use analog circuits. The gap exists between the slower growth in design productivity over manufacturing productivity, and analog circuits are proving resistant to design automation and still require – and get – much handcrafting. These were the observations of the panel of EDA and System-On-Chip experts gathered at International Solid-State Circuits Conference.
Moderated by Jan Rabaey from the University of California, Berkeley, the panel concluded on a generally optimistic note – that in the digital domain and with heavy re-use of previously designed circuit blocks, it would be possible to design such chips in close to 100 days. "I think we can end on a positive note," said Rabaey. "If you stick to certain methods you can do the back end. But there are lot of issues at the front end."
The academic community was represented by Asad Abidi, a professor at the UC Los Angeles; Hugo De Man, from Catholic University of Leuven (Belgium); and Alberto Sangiovanni-Vincentelli from the UC Berkeley. The industrial experts were Raul Camposano, Chief Technology Officer of Synopsys Inc. (Mountain View, California); Andrea Cuomo, Vice President of Advanced Systems Technology at STMicroelectronics (Geneva, Switzerland); Mehdi Hatamian, Director of DSP Technology at Broadcom Corp. (Irvine, California); and Harry Veendrick, Philips Research (Eindhoven, Netherlands).
Hatamian gave the answer "yes, maybe," adding, "It depends on how much memory there is, what it's going to do, and does it only have to work once to allow an ISSCC paper to be written." He then stressed that the best chance of success came with the right people. Sangiovanni-Vincentelli argued that ASICs are now going to disappear rapidly in favor of platforms of parameterizable hardware and software such as the Nexperia platform from Philips, aimed at different applications.
Abidi repeatedly stressed the special role of analog and why it could thwart attempts to design complex chips at speed. "So ban the analog and RF to an island in multichip module package," was De Man's response. Sangiovanni-Vincentelli interjected, "If we want to step up to the system level, we must solve the analog problem. We must learn how to re-use it, and then you can spend a long time on it. I believe you can trade off performance versus reusability." However, Abidi pointed out, "The one thing the customer wants is more performance – we seldom find the opportunity for re-use."
It was left to De Man to raise the specter of software. His point was that while larger on-chip memories might make hardware design easier and faster, this implied megabytes of embedded processor code. De Man pointed out there was insufficient software productivity to write the code without throwing hundreds of software engineers at the problem.
"600 Mbytes of software is about 600,000 lines of C++ code," he said, before adding that a software engineer's typical productivity is 20 to 30 lines a day.
So as with the doors of opportunity, as the design productivity gap closes, another gap opens.
Peter Clarke
EETimes
Copyright©2001 by CMP Media LLC, 6000 Community Drive, Manhasset, NY 11030. Reprinted from EETimes with permission.