Solid-State Circuits Award to CMOS Circuit Pioneers

Robert W. Krambeck	Hung-Fai Stephen Law

The 2000 Solid-State Circuits Award recipients, Robert W. Krambeck and Hung-Fai Stephen Law, are being honored for pioneering the introduction and implementation of domino CMOS logic. This form of dynamic logic requires only a single clock and offers the highest speed possible in CMOS logic, yet it is completely free from race conditions. It was the starting point for a new approach to CMOS logic, and its many variants are now indispensable in areas such as the design of high-performance microprocessors.

From the beginning of MOS technology, dynamic circuits have been used in DRAMs, shift registers, PLAs, and other highly regular digital arrays. Because of the potential savings in power, significant effort was devoted to the development of dynamic circuits for realizing general-purpose NMOS logic throughout the 1970s. This work typically resulted in complex multistage logic circuits. Moreover, race conditions in these circuits would result in errors unless multiple clocks were used to carefully propagate information from stage to stage. The need for multiple, carefully controlled clocks often led to disappointingly slow circuits.

In 1977, Krambeck, Law, and Charles M. Lee (deceased) conceived an elegant and definitive means of employing dynamic circuit techniques to reduce the area and improve the performance of digital circuits implemented in CMOS technology. Until the late 1970s, commercial microprocessors were realized with NMOS technology. CMOS emerged as an alternative to NMOS to conserve power without the complexity associated with dynamic NMOS circuitry. But CMOS gates were designed as static circuits, which were generally regarded as too large, and therefore too costly, for anything but niche markets. Krambeck et al. felt even then that CMOS was the wave of the future, but they realized that it would be necessary to eliminate as many of the redundant PMOS transistors as possible. Dynamic logic was the perfect means of accomplishing this, if it could be made reliable and simple enough. They then had the counterintuitive insight that the required simplicity could be obtained by adding a static CMOS inverter to the output of a precharged dynamic gate. The inverters were compact, low power, and could be used as buffers to drive large load capacitances, which in turn permitted the size of all logic transistors to be minimized. An even deeper insight was that all stages of logic would have inputs that were precharged to zero, so that only a single clock was needed. When the cascade of domino CMOS gates is clocked, no stage transitions until its predecessor has done so. Thus, information ripples down the cascade of gates at full speed, like a row of falling dominos.

Since domino CMOS gates are noninverting, they do not provide a universal set of logic elements. They are, however, by their nature input/output-compatible with static CMOS gates. Therefore, most logic functions can be implemented with domino CMOS either alone or in combination with a small amount of static CMOS logic. Krambeck, Law, and Lee first used domino CMOS in the design of an 8-bit arithmetic logic unit (ALU) and then in a subsequent 32-bit ALU. They discovered that the critical fast-carry path in these circuits could be implemented in domino CMOS together with a single static exclusive-OR gate at the output. This implementation proved to be twice as fast as a static CMOS realization and substantially more compact. The results of this work were published in 1981, and a patent was granted in 1983.

The work of Krambeck, Law, and Lee has proven to be the impetus for much subsequent work on high-performance digital CMOS logic design. Domino CMOS and its derivatives are now used in far more complex logic systems than were described in the original work, employing multiple static inverters and clocks as well as differential circuits in order to achieve the highest possible speed. These techniques are now widely exploited in high-speed VLSI circuits such as microprocessors and digital signal processors.

The recipients of the Solid-State Circuits Award solved an important and highly visible circuit problem that was becoming a major obstacle to the continued exponential growth in the scale of digital circuit integration. Their solution was a breakthrough in circuit design, and it has been widely praised and adopted by their colleagues.

Robert Krambeck is retired from Compaq Computers and cruising the North America's coasts west to east through the Panama canal in his sailboat, "Best of Times." He has no land-based residence at the moment. He began his professional career at Bell Laboratories after receiving a Ph.D. in Electrical Engineering from Carnegie Mellon University. As a Member of the Technical Staff at Bell Labs from 1968 to 1977, Krambeck did original work on trapping effects in silicon buried-channel devices as well as charge-coupled structures. From 1977 to 1982, as the Supervisor of Microprocessor Design, he managed the development of AT&T's 8- and 32-bit microprocessor families. From 1982 to 1989, he was responsible for the development of design methodologies for standard and custom ICs. The last 6 years of Krambeck's career at Bell Labs were spent as the Head of the Custom IC Design Department, where he was responsible for the development of FPGA silicon and software as well as integrated circuits for local area networks. From 1995 to 1998, Krambeck was the manager of Processor Development at Tandem Computers, where he supervised a 40-member staff developing fault-tolerant computers and the associated application-specific ICs.

After receiving a Ph.D. in Electrical Engineering from Columbia University, Steve Law joined Bell Laboratories. As a Member of the Technical Staff and then as a supervisor, he conceived and then developed the gate matrix approach to symbolic layout, coinvented domino CMOS logic, and contributed to the design of 32-bit CMOS microprocessors. As founder and R&D director at Cadence Design Systems from 1983 to 1990 Law, developed SKILL, a layout editor, layout automation tools, and logic synthesis tools. Between 1990 and 1994, he served in a variety of roles at Aptix Corp., including co-founder, vice president, COO, and director. There Law was responsible for the introduction and support of the new FPIC multichip system and later managed company operations. As a Vice President of Optivison, Inc. from 1995 to 1997, Law's responsibilities included the design, introduction, and support of a series of leading-edge MPEG video compression products. Presently, Steve Law is the Vice President of Alaris, Fremont, CA. At Alaris, Law is responsible for ASIC development, foundry arrangements, and Asian OEM sales.

The seminal paper relevant to this award is "High-speed compact circuits with CMOS," in Journal of Solid-State Circuits, pp. 614Ð618, June 1982. This is a more complete version of a paper first presented at ESSCIRC in 1981. It is available now for $22.95 through Ask *IEEE, the document delivery service of the IEEE. Fax: (303) 758-1138; Tel: (303) 759-2226; Within the U.S.: 1-(800) 949-4333; Email: askieee@ieee.org.

Bruce Wooley
Vice President

IEEE Solid-State Circuits Society
wooley@ee.stanford.edu

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