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Question 007-07: “What methodology can be used for quantum approach to transport in nano devices which utilizes the minimum computation time?”Question 011-07: What is the good surface passivation process on the Ge (SiGe) substrate?
Question 008-07: How I can change my user name of the IEEE account?
Question 021-08: What are Quantum Dots & Wires? Which phenomenon leads to the study of Quantum Dots & Wires? How the problems are solved using Quantum Dots & Wires in comparison with conventional device?
Question 002-07: Looking at energy band diagram of SONOS memory devices
(ED-53 (2006), No. 4, pp 654-662), under programming, which meant positive
voltage was applied to control gate (P-subs), but control gate has lower
level than substrate. Why? should it be reversed ?
Answer 002-07: The energy band diagrams shown are electron energy band
diagrams. Hence electron energy (W) increases in the upwards direction while
potential (V) increases in the downwards direction as a result of the
negative charge (-q) of the electron, since W = -qV. Since the control gate
is biased positively with respect to the substrate in the program mode, we
would expect the energy level of the control gate to be lower than that of
the substrate. [back to top]
Question 007-07: “What methodology can be used for quantum approach to transport in nano devices which utilizes the minimum computation time?”
Answer 007-07: The specific method chosen depends on the problem being addressed. Among the many methods for quantum transport, one method has been broadly accepted; the so-called non-equilibrium Green's function (NEGF) method. This method has a firm basis in theory and has been successfully applied to problems from quantum transport in molecules, carbon nanotubes, semiconductor nanowires, nanoscale MOSFETs, spintronic devices, and more. For an introduction to the approach, visit www.nanoHUB.org, search "Datta" and look for the series of four lectures, "Concepts in Quantum Transport."
For simple nanodevices such as carbon nanotubes, the NEGF approach is often quite efficient, but for nanoscale MOSFETs, for example, the computational burden can be very large. (The NEGF approach is equivalent to solving the Boltzmann Transport Equation with one additional dimension.) For nanoscale MOSFETs, the so-called "density-gradient" or "effective potential" approach is often used. This method can be implemented by an added term to the drift-diffusion equation, and it can be used to "include" quantum transport" in Monte Carlo simulation. It is much more efficient than NEGF simulation, but needs to be carefully used and benchmarked against more rigorous methods such as NEGF. [back to top]
Question 001-07: Why it is not possible to measure the built-in voltage of a PN junction using a voltmeter?
Answer 001-07: The built-in voltage of a PN junction can be considered as the contact potential between two dissimilar metals. When the leads of a voltmeter are contacted to either side of a PN junction, the contact potential between the voltmeter lead and P-type material, contact potential of the PN junction, and the contact potential between the N-type material and the voltmeter lead form a closed loop. Since the sum of all contact potentials in a closed loop is zero, the built-in voltage can not be measured by a voltmeter. (Reference: Operation and Modeling of the MOS Transistor, chapter 1, 2nd edition, by Y. Tsividis). [back to top]
Question 011-07: What is the good surface passivation process on the Ge (SiGe) substrate?
Answer 011-07: The answer to this question appears to fall in the proprietary domain and experts approached so far are reluctant to answer it. Hence, we are unable to provide an answer to this question at this time. If any of the readers have a possible lead, please send your response to samar@ieee.org. [back to top]
Question 008-07: How I can change my user name of the IEEE account?
Answer 008-07: To change your user name on your IEEE account, please visit the following website for instructions, http://www.ieee.org/web/aboutus/help/task/my_account/changepw.html [back to top]
Question 010-07: “I'm embedding chips (processed CMOS, 0.5 ... 2 mm on each side) into PMMA slides with appropriately sized recesses. Can you recommend a leveling agent to planarize the surface after embedding (e.g. for subsequent metallization).”
Answer 010-07: The answer to this question is of proprietary nature and the experts contacted provided only the following note: “The leveling agent before metallization is generally sulfuric acid system, for example, H2SO4+H2O2, NaHSO4, H2SO4, Na2S2O8 etc." If any of the readers have a possible lead to a more detailed answer to this question please send a response to samar@ieee.org. [back to top]
Question 003-07: Can someone show the derivation of BVCER of a bipolar transistor when a resistor RBE is connected between the emitter and base? We are measuring the breakdown voltage between the collector and emitter with a resistor between the emitter and base.
Answer 003-07: The collector-emitter breakdown voltage, BVCER with a base resistor RB connected to the base is used to define reliable operating conditions for bipolar junction transistors exceeding BVCEO. The expression for BVCER is given by:
Where VB'E' = internal base-emitter voltage, VBE = external base-emitter voltage, BVCBO = collector-base breakdown voltage with emitter open, vt = thermal voltage, Is = emitter-base diode saturation current, BETA = transistor gain, and m is a fitting parameter. The detailed derivation can be found in Proc. of BCTM 2005, pp. 33-36. [back to top]
Question 005-07: Most varactor diodes are made from a P+N junction. What is the reason an N+P structure is usually not considered although it could provide a faster device when operated in applications where some direct bias is involved such as SRD multiplier?
Answer 005-07: Here, we assume that the author meant integrated Varactor diodes in RF circuit on CMOS, or BiCMOS, or SiGeBICMOS processes. One of the reasons to select P+N diodes instead of N+P is its better isolation performance and compatibility with standard regular process without adding extra cost in device fabrication.
In addition, the design considerations for Varactor diodes include minimizing the series resistance and junction leakage current to achieve high quality factor along with the optimization of junction abruptness. Since the resistivity of N-region is lower than the P-region with the same doping concentration, the series resistance of the P+N Varactor is lower than the N+P diodes of similar doping profiles. Similarly, since the diode leakage current is dominated by the minority carrier diffusion, the leakage current of P+N Varactor with low diffusivity hole as the primary minority carriers is lower than the N+P Varactor with high diffusivity electrons as the primary minority carries with similar doping profiles. Hence, P+N Varactors are preferred. [back to top]
Question 004-07: I am trying to fabricate a PDMS microchannel over glass/silicon dioxide/alumina-stacked waveguide surface. I am facing problems in spin coating PDMS and then later patterning it for a dry plasma etching? Please tell me what is the best procedure to pattern and etch PDMS without any harm to the alumina surface?
Answer 004-07: The only way you can do this is by an atomic layer deposition (ALD) process and not by spin coating. You need about 200 – 500 nm of thickness and it is only possible by ALD. ALD film ensures coverage on all sides of a released MEMS device and is done at a relatively low temperature (down to 150°C). The ALD film thickness can be precisely controlled as each reaction cycle deposits approximately one monolayer of atoms. Also, the idea of alumina is great for protecting MEMS. [back to top]
Question 012-07: When doing device characterization, we often test the linear threshold voltage (Vth) and saturation Vth, I know the condition for saturation is Vs = Vb = 0, Vd = Vdd, and sweep Vg to find Vth with Gm max method, but I want to confirm if the condition for linear Vth is Vds = 0.1V? And, would you please help to explain why we need to test those two items? What is their difference?
Answer 012-07: In order to extract the linear Vth (Vt,lin) by linear extrapolation method at maximum Gm, the drain voltage must be as small as possible to maintain a uniform charge density in the inversion channel from the source to drain (that is similar to resistor with constant sheet resistance from source to drain) and negligible bulk depletion charge effect due to Vd. Therefore, a small value of Vds = 50 mV is preferred for advanced technologies, though Vds = 100 mV is typically used in practice.
The saturation Vth (Vt,sat) extracted by the quadratic extrapolation method is different from Vt,lin because of the drain induced barrier lowering (DIBL) effect at high Vd, especially, for short channel devices. As a result, the values of Vt,lin and Vt,sat are different. And, the magnitude of (Vt.lin – Vt,sat) is the measure of DIBL effect that contributes to the off-state leakage current in MOSFETs. Therefore, both Vt,lin and Vt,sat need to be measured to check the DIBL effect and robustness of device architecture. [back to top]
Question 013-07: Is there a multi-particle Monte-Carlo simulator available in the public domain to simulate noise in semiconductor devices?
Answer 013-07: There are many multi-particle Monte Carlo simulators that can treat noise. However, to the very best of my knowledge, no public domain Monte Carlo device simulator with noise analysis capabilities is currently available. In general, though, any MC simulator can treat noise. But, one must be careful to distinguish numerical noise, which varies as 1/sq-rt(N), from real noise. The complexity of the problem in terms of the microscopic model and the range of validity for the concept of noise to be applied only allows for the set up of Monte Carlo simulators specific to the problem at hand.
The number of research groups with an internationally recognized reputation on the subject is very few. Concerning Monte Carlo simulation of noise in devices, several papers have appeared in the literature: one of the most active research groups is the Electronics Group at the University of Salamanca, in Spain (http://www.usal.es/~gelec/ingles/webgrupo.htm). [back to top]
Question 014-07: I am looking for an interesting/hot shot topic for my theses so your suggestions are welcome since I could not find anyone around who is really updated about electronic devices. Mainly I am interested in Device modeling, novel devices & quantum phenomena in practical nano-structures. Please suggest even if the topic is more than undergrad level since I am already planning to go for graduate study.
Answer 014-07: As an undergraduate you probably see mostly super-simple devices like diodes or simplified state-of-the-art MOS devices that have been reduced to their SPICE equivalent models. In preparing for graduate school and speaking of devices, there are several kinds of still basic device types that will more broadly prepare you for the future:
1) photo-diode effect (i.e. solar cells and photo-detectors)
2) bipolar transistors (vs. MOS majority carrier effects, minority carrier devices)
3) parasitic effects in general (i.e. "latchup" in circuits and electro-static discharge (ESD) protection)
This is a rather broad set of devices and issues, beyond the basic diode-MOS world view. But, the physics that come from minority carrier effects is important. The book by Prof. Streetman, Solid State Electronic Devices, Prentice Hall, is a good place to start (and can keep you busy for some time). [back to top]
Question 016-08: I want to know, in order to find the on-resistance of a power VDMOSFET, what should be the values of gate voltage and drain voltage?
Answer 016-08: Typically, the on resistance (Rdson) of VDMOSFETs is measured at the bias point: drain voltage, Vds = 0.1 V (or 0.2 V) and gate voltage, Vgs = Vdd – 10% of Vdd, where Vdd is the supply voltage. Some people in the field have, also, used Vgs = Vdd. [back to top]
Question 018-08: What is the best way to derive an expression for the average thermal velocity of an electron assuming Fermi-Dirac Statistics? Are there any literatures with the derivation?
Answer 018-08: On thermal velocity: First of all, it is important to recognize that there are different ways to define a "thermal" velocity and that it is important to understand which thermal velocity is appropriate for the problem being addressed. For example, for a non-degenerate semiconductor in equilibrium (in three dimensions) with parabolic energy bands, the average kinetic energy of electrons in the conduction band is (3/2)(kB)(T), where kB is the Boltzmann’s constant and T is the temperature in Kelvin, so that:
(1/2)(m*)
Accordingly, the "rms average thermal velocity" is:
v_thermal (rms) = sqrt(
On the other hand, we could ask another question: What is the average velocity of electrons directed in the +x direction for a non-degenerate semiconductor in equilibrium? (Note that the overall average velocity is zero, because we are in equilibrium, but we can compute the average velocity of those in the +x direction, which is equal and opposite to the average velocity of those in the -x direction). We call this "thermal velocity" the "unidirectional thermal velocity, v_T."
A derivation shows: v_T = sqrt[(2)(kB)(T)/(pi)(m*)].
This velocity appears in thermionic emission problems. In fact, for thermionic emission, people frequently talk about the "Richardson thermal velocity, v_R” and v_R = v_T/2.
In general, these results depend on whether the electrons are free to move in 1, 2, or 3 dimensions, and if the semiconductor is degenerate, they involve Fermi-Dirac integrals (different ones depending on the dimensionality).
The only discussion and derivation of these results that I am aware of is in Lecture 3 of Professor Mark Lundstrom's course "Electronic Transport in Semiconductors," which is available online at: http://cobweb.ecn.purdue.edu/~ee656/lectures.html. [back to top]
Question 019-08: When a reverse (or forward) voltage is applied to a pn junction diode, the equilibrium condition is disturbed. One of the main consequences of such an external voltage is the splitting of quasi-Fermi levels. Such a splitting extends only around the junction; away from the junction, both the electron and hole quasi-Fermi levels lie at the majority carrier Fermi level.
Accordingly, when a source voltage Vsb is applied to the source of an MOS transistor with respect to the body, the electron quasi-Fermi level on the source gets separated from the hole quasi-Fermi level on the substrate by an amount of qVsb. But, such a splitting should not continue for the entire channel and it should be restricted only around the source-body junction. However, we always assume that such splitting continues throughout the entire channel region. Why?
Answer 019-08: The electron (EFn) and hole (EFp) quasi-Fermi levels (QFLs) in a biased pn junction merge away from the metallurgical junction where the excess carrier densities (positive or negative) go to zero. Generally, the minority-carrier QFL away from the junction is graded to support the minority-carrier current because of low carrier density, while the majority-carrier level is virtually flat (except when ohmic drops are significant). Such a QFL description applies to the source region of a MOSFET with a bias (VBS) applied to the body-source junction. However, the situation on the channel side of the junction is a bit more complicated. Consider an n-channel MOSFET with a nonzero VBS and, initially, the drain-source voltage VDS = 0. At the body-source junction, (EFn – EFp) = qVBS. If the gate is biased above threshold, the electron-inversion layer can be considered an extension of the n-side of the junction, along which EFn is flat (since no channel current flows for VDS = 0). Since there is no hole current either, EFp can be assumed flat along the channel as well. Thus, (EFn – EFp) = qVBS along the channel is a reasonable assumption. For VDS > 0, EFn is lowered at the drain junction, and (EFn – EFp) = q(VBS – VDS) there. The noted separations of the QFLs at the source and drain ends of the channel define the VBS dependences of the MOSFET current. Note, however, that below the channel region and toward the body contact (in a bulk MOSFET) the QFLs on both sides of the body-source junction behave normally, as described above. [back to top]
Question 021-08: What are Quantum Dots & Wires? Which phenomenon leads to the study of Quantum Dots & Wires? How the problems are solved using Quantum Dots & Wires in comparison with conventional device?
Answer 021-08: When an electron is confined spatially on a scale that is comparable to its wavelength, then quantum mechanics controls its properties. This is the reason for energy level in atoms and molecules. It is also possible to artificially confine electrons by producing a very small "dot" of a semiconductor. The energy levels for the electron can then be engineered. For example, the wavelengths (i.e. colors) of light that are absorbed can be engineered by the size and shape of the quantum dot. Quantum dots of this kind have applications in medical diagnostics (for optical labeling). They are also being explored as a possible avenue for increasing the efficiency of solar cells and of thermoelectric materials.
Quantum wires are similarly-engineered quantum structures. Instead of confining electrons in all three dimensions as in a quantum dot, electrons are confined in two dimensions but are free to move in a third dimension. This produces a wire in which electrons behave as one-dimensional particles. Again, the quantum confinement changes the electronic properties (e.g. the density-of-states) in ways that may be beneficial to transistors performance, thermoelectrics, and possibly other applications. [back to top]
