Question 019-08: When a reverse (or forward) voltage is applied to a pn junction diode, the equilibrium condition is disturbed. One of the main consequences of such an external voltage is the splitting of quasi-Fermi levels. Such a splitting extends only around the junction; away from the junction, both the electron and hole quasi-Fermi levels lie at the majority carrier Fermi level.

Accordingly, when a source voltage Vsb is applied to the source of an MOS transistor with respect to the body, the electron quasi-Fermi level on the source gets separated from the hole quasi-Fermi level on the substrate by an amount of qVsb. But, such a splitting should not continue for the entire channel and it should be restricted only around the source-body junction. However, we always assume that such splitting continues throughout the entire channel region. Why?

Answer 019-08: The electron (E_Fn) and hole (E_Fp) quasi-Fermi levels (QFLs) in a biased pn junction merge away from the metallurgical junction where the excess carrier densities (positive or negative) go to zero. Generally, the minority-carrier QFL away from the junction is graded to support the minority-carrier current because of low carrier density, while the majority-carrier level is virtually flat (except when ohmic drops are significant). Such a QFL description applies to the source region of a MOSFET with a bias (V_BS) applied to the body-source junction. However, the situation on the channel side of the junction is a bit more complicated. Consider an n-channel MOSFET with a nonzero V_BS and, initially, the drain-source voltage V_DS = 0. At the body-source junction, (E_Fn ­– E_Fp) = qV_BS. If the gate is biased above threshold, the electron-inversion layer can be considered an extension of the n-side of the junction, along which E_Fn is flat (since no channel current flows for V_DS = 0). Since there is no hole current either, E_Fp can be assumed flat along the channel as well. Thus, (E_Fn – E_Fp) = qV_BS along the channel is a reasonable assumption. For V_DS > 0, E_Fn is lowered at the drain junction, and (E_Fn – E_Fp) = q(V_BS – V_DS) there. The noted separations of the QFLs at the source and drain ends of the channel define the V_BS dependences of the MOSFET current. Note, however, that below the channel region and toward the body contact (in a bulk MOSFET) the QFLs on both sides of the body-source junction behave normally, as described above. [top of page]

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Question 020-08: With reference to QuestEDS ‘Answer 019-08’ that is valid for the above threshold condition only, what is the reason for the same in the subthreshold condition? In particular, if we consider a three-terminal MOS structure, it is assumed that on application of a nonzero V_SB the QFL throughout the entire channel splits (by qV_SB) even in the weak inversion (subthreshold) where we cannot assume that the entire channel region is an extension of the n+ source region?

Answer 020-08: A more general response to Question #QE019-20, and to this one, follows from first noting that an applied V_BS (to an n-channel MOSFET) lowers the Fermi level at the body contact [E_F(B)] below that at the source contact [E_F(S)] by qV_BS. Then, for V_DS = 0, the assumption that (E_Fn – E_Fp) = qV_BS along the channel (for negligible ohmic drops) is tantamount to assuming that E_Fp is flat, equal to E_F(B), from the body contact to an arbitrary point in the channel and that E_Fn is flat, equal to E_F(S), from the source contact to the same channel point. These assumptions are reasonable for inversion conditions, including weak inversion, because a flat QFL obtains for relatively high carrier density and/or relatively low current. (For V_BS < 0, the assumption has to be qualified a bit, just like in the space-charge region of a reverse-biased pn junction where quasi-equilibrium is not a valid assumption.) However, for accumulation, the flat-E_Fn assumption is clearly not valid. In this case, which is not relevant to the characterization of the MOSFET channel current, the QFLs on both sides of the biased body-source junction behave normally, as in an isolated pn junction, with (E_Fn – E_Fp) = qV_BS only near the metallurgical junction. [top of page]

Question 003-07: Can someone show the derivation of BVCER of a bipolar transistor when a resistor RBE is connected between the emitter and base? We are measuring the breakdown voltage between the collector and emitter with a resistor between the emitter and base.

Answer 003-07:  The collector-emitter breakdown voltage, BVCER with a base resistor RB connected to the base is used to define reliable operating conditions for bipolar junction transistors exceeding BVCEO. The expression for BVCER is given by:

Where VB'E' = internal base-emitter voltage, VBE = external base-emitter voltage, BVCBO = collector-base breakdown voltage with emitter open, vt = thermal voltage, Is = emitter-base diode saturation current, BETA = transistor gain, and m is a fitting parameter. The detailed derivation can be found in Proc. of BCTM 2005, pp. 33-36. [top of page]

Question 001-07: Why it is not possible to measure the built-in voltage of a PN junction using a voltmeter?

Answer 001-07:  The built-in voltage of a PN junction can be considered as the contact potential between two dissimilar metals. When the leads of a voltmeter are contacted to either side of a PN junction, the contact potential between the voltmeter lead and P-type material, contact potential of the PN junction, and the contact potential between the N-type material and the voltmeter lead form a closed loop. Since the sum of all contact potentials in a closed loop is zero, the built-in voltage can not be measured by a voltmeter. (Reference: Operation and Modeling of the MOS Transistor, chapter 1, 2^nd edition, by Y. Tsividis). [top of page]

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Question 005-07: Most varactor diodes are made from a P+N junction. What is the reason an N+P structure is usually not considered although it could provide a faster device when operated in applications where some direct bias is involved such as SRD multiplier?

Answer 005-07: Here, we assume that the author meant integrated Varactor diodes in RF circuit on CMOS, or BiCMOS, or SiGeBICMOS processes. One of the reasons to select P+N diodes instead of N+P is its better isolation performance and compatibility with standard regular process without adding extra cost in device fabrication.

In addition, the design considerations for Varactor diodes include minimizing the series resistance and junction leakage current to achieve high quality factor along with the optimization of junction abruptness. Since the resistivity of N-region is lower than the P-region with the same doping concentration, the series resistance of the P+N Varactor is lower than the N+P diodes of similar doping profiles. Similarly, since the diode leakage current is dominated by the minority carrier diffusion, the leakage current of P+N Varactor with low diffusivity hole as the primary minority carriers is lower than the N+P Varactor with high diffusivity electrons as the primary minority carries with similar doping profiles. Hence, P+N Varactors are preferred. [top of page]

Question 002-07: Looking at energy band diagram of SONOS memory devices (ED-53 (2006), No. 4, pp 654-662), under programming, which meant positive voltage was applied to control gate (P-subs), but control gate has lower level than substrate. Why? should it be reversed ?

Answer 002-07: The energy band diagrams shown are electron energy diagrams. Hence electron energy (W) increases in the upwards direction while potential (V) increases in the downwards direction as a result of the negative charge (-q) of the electron, since W = -qV.  Since the control gate is biased positively with respect to the substrate in the program mode, we would expect the energy level of the control gate to be lower than that of the substrate. [top of page]

Question 022-08: What is the primary advantage to fabrication of a GaAs or GaN HEMT on a semi-insulating substrate versus a conducting substrate? Which transistor performance properties are most influenced by the electrical properties of the substrate?

Answer 022-08: The major advantage of fabricating a GaAs or GaN HEMT on a semi-insulating substrate is that since a semi-insulating substrate has very high resistivity both active and passive components can be integrated into one substrate with a minimum parasitic capacitance compared to a conductive substrate. The extra parasitic capacitance of a conductive substrate would increase the undesirable device capacitances and hence affect the high frequency characteristics of the transistors. One would notice these when studying the small-signal parameters of the device. In addition, it would increase the line capacitance of the circuits causing extra delay. Also, if the transistor is used for microwave applications, a conducting substrate will cause too much loss while a non-conducting substrate will not. [top of page]