The world's leading professional association
for the advancement of technology
Text size »A  A  A  
 » EDS Home
 » EDS Publications Home
 » EDS Publications Office
 » Transactions on Device and Materials Reliability (T-DMR)
 » T-DMR Editor-in-Chief & Editors
 » T-DMR Call for Papers
 » T-DMR Special Issue Calls/Announcements
 » T-DMR Information for Authors
 » IEEE Guidelines for Authors
 » IEEE Copyright Information
Richard Blish
 

 Richard Blish
Spansion
Quality & Reliability Eng
915 De Guigne, Mail Stop 33
Sunnyvale, CA 94088-3453, USA
Tel: +1 408 616 6788
Fax: +1 408 616 8174
E-Mail: richard.blish@amd.com


Richard Blish received a B.S. in Physics (1963) and a Ph.D. in Materials Science (1967) from the California Institute of Technology. He spent 1967-69 at Bell Labs correlating electrical properties of diode arrays to crystalline damage detected by X-ray topography. 1969-80 were at Signetics, working on XRF, SEM, microprobe, metallography, chromatography and plasma etching. 1980-94 were at Intel in a variety of management roles in Package Reliability. 1995 to present have been at AMD, currently as an AMD Fellow in Reliability Engineering. Rich has 18 patents (24 pending) and 20 publications, winning awards for paper quality at IRPS & ECTC. Rich is a past General Chair and Chairman of the Board of IRPS & chaired the SEMATECH RTAB for 2000.



Please scroll to see more.

 


IEEE Home   |   Sitemap   |   Search   |   Privacy & Security   |   Terms & Conditions
 
IEEE Logo