Dr. Robert E. Fontana, Jr. and Prof. Bruce Wooley will speak at a Technical Seminar presented by the Denver Chapter in cooperation with the Colorado State University Department of Physics in Fort Collins, Colorado on 10 November 2005.

Dr. Robert E. Fontana	Prof. Bruce Wooley

Dr. Fontana is a research staff member within the recording head processing function of the San Jose Research Center, Hitachi Global Storage Technologies (GST) in San Jose, California; Dr. Wooley is the Robert L. and Audrey S. Hancock Professor of Engineering and the Chairman of the Department of Electrical Engineering at Stanford University.

 "Micro Fabrication Techniques for Magnetic Information Storage Devices: From Bubbles to Thin Film Recording Heads to Nano Magnetic Structures"

In this lecture, Dr. Fontana will examine magnetic device structures from the perspective of thin film processing, comparing techniques for forming magnetic device structure minimum features with semiconductor processing. He will also project storage density growth in both magnetic memories and magnetic recording using solid-state semiconductor roadmaps, and compare the "nano" characteristics (thickness and length scale) of next generation magnetic thin film heads and magnetic memory devices with solid-state semiconductor designs.

"Due to dramatic decreases in the bit cell size for storage products incorporating magnetic device structures and non-volatile memory products," he said, "the last 25 years have seen 10³ to 10⁵ increases in information storage densities. The future manufacture of cost-effective magnetic device-based information storage products will continue to present nano-scale processing challenges." These will be explored at the conclusion of his talk.

"Cascaded Noise-Shaping for Oversampling A/D and D/A Conversion"

"Through the exchange of resolution in time for that in amplitude, noise-shaping sigma-delta modulators offer an efficient means of integrating precision A/D and D/A converters in scaled CMOS VLSI technologies," Dr. Wooley said.  "Cascade architectures are a robust approach to extending the performance of such modulators to signal bandwidths of several MHz as their design is straightforward and they are immune to stability issues that must be addressed in the design of higher-order modulators employing a single quantizer.  At signal bandwidths of tens of kHz or less, high oversampling ratios can be used to realize sigma-delta modulators with performance that is insensitive to technology limitations.  However, to meet the demands of emerging communications applications, the performance of cascaded oversampling modulators with low oversampling ratios has been extended to enable the digitization of signals with bandwidths of several MHz, centered at either dc or at intermediate frequencies as high as 20 MHz.  Distributed noise shaping and multilevel quantization can be used to significantly lower the oversampling ratio needed to achieve a specified precision, thus increasing the signal bandwidth that can be digitized within the constraints of a given technology.  Digital cascaded noise shaping modulators can be used for D/A conversion, and means have been found to combine such architectures with semi-digital reconstruction filtering."