John McNeill, Associate Professor of Electrical and Computer Engineering at Worcester Polytechnic Institute (WPI) and Michael Coln and Brian Larivee of Analog Devices (ADI) received the Lewis Winner Award at the 2006 ISSCC for their 2005 ISSCC paper “A split-ADC architecture for deterministic digital background calibration of a 16b 1 MS/s ADC.”

From left, Tim Tredwell, ISSCC Executive Chair, Brian Larivee, Dr. Michael Coln, Dr. John McNeill.

Chip Summary
The “split-ADC” architecture enables the use of a deterministic digital calibration procedure that operates continuously in the background and requires fewer than 10,000 conversions to complete calibration. This architecture, demonstrated in a 16b, 1 MS/s algorithmic ADC, is shown in the figure to the right. The analog sub-system of the ADC was implemented in 0.25 micron CMOS, consumes 105 mW, and has a die size of 1.2 x 1.4 mm².

Dynamics of the Project
Although this project started in the summer of 2002, McNeill's relationship with Analog Devices began a decade earlier.  As a PhD student at Boston University from 1991-1994, he worked with Larry DeVito's PLL group to develop a theoretical framework for understanding jitter in ring oscillators and guiding design to meet specific noise requirements; this work was published in the Journal of Solid-State Circuits in 1997 (dx.doi.org/10.1109/4.585289).

When McNeill's turn for a sabbatical leave from WPI came up in the 2002-3 academic year, he contacted DeVito and asked if he knew of any good problems to work on at ADI.  At the same time, Mike Coln in ADI's Precision Nyquist Converter Group was looking for a "breakthrough" in ADC design: an innovative architecture that would explicitly take advantage of CMOS scaling by relaxing requirements on analog circuitry and moving as much complexity as possible into the digital domain.  Working in Coln's group at ADI, McNeill completed the top-level architecture design in the fall of 2002; circuit design and layout were completed by the fall of 2003.  As McNeill returned to his teaching and research duties at WPI in 2003, Brian Larivee carried out the process of integrating the analog test chip with the FPGA implementing the digital calibration algorithm.   The test and evaluation process was completed in time to submit the paper for ISSCC in September 2004.

The collaborative relationship between WPI and Analog Devices is continuing in research toward applying the split ADC concept to other types of ADCs.  In addition to funding from ADI for this work, McNeill was also awarded a grant from NSF in 2005 to support further research.

John McNeill joined the ECE faculty at WPI in 1994.  Since 1998, he has been director of the Center for Analog and Mixed Signal Integrated Circuit Design at WPI, (http://ece.wpi.edu/analog/center.html), a consortium of industry sponsors supporting undergraduate projects and graduate research in the area of analog and mixed signal integrated circuit design.  In 1999 he received the WPI Trustees’ Award for Outstanding Teaching. He received an A.B. degree from Dartmouth College in 1983, an M.S. degree from the University of Rochester in 1991, and a Ph.D. from Boston University in 1994.  From 1983 to 1990 he worked in industry in the design of high speed, high resolution analog-to-digital converters and low noise interface electronics used in high speed, wide dynamic range imaging systems. 

Mike Coln joined Analog Devices in 1988, after earning a PhD from MIT. Since then, he has been involved in design, leadership, and mentoring roles, contributing to all areas of precision data converter development within the company. A holder of 12 patents, Coln was the chief architect of ADI’s PulSAR® analog-to-digital-converter (ADC) family, which overcame perceived architectural barriers then boxing-in the specifications of speed, resolution, power consumption, and size of successive-approximation converters. The PulSAR self-calibrating architecture was the first to enable 16-bit ADCs to reach throughput of 1 Msps (million samples per second), and it resulted in the first SAR ADC to reach 18-bit resolution.  In 2005, Coln was named an Analog Devices Fellow, the highest level of achievement for a technical contributor at Analog Devices, Inc.

Brian Larivee has been working for Analog Devices since 2003 as a design engineer for the Precision Nyquist Converters group.  He received the BSEE and MSEE degrees from the University of Michigan in May 2002 and December 2002, respectively.  His development interests are in the areas of Nyquist-rate converter design and low-power analog integrated circuit design techniques.