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Coming 2Q 2009: “Active-RC Filters for the Analog Front End Part 2” by George Moschytz, sponsored by the IEEE Circuits and Systems Society In this course, we shall introduce analytical tools, which are useful for the formulation of criteria with which we can decide which inductorless active-RC filters of the kind presented in the first course (or of other similar kinds) are most suitable for the front end of mixed-mode integrated-circuit system chips. These tools will enable us to select and characterize optimum filter realizations for the analog front end. With the filters selected according to these criteria, we shall then go through the detailed steps necessary for their DESIGN. They represent typical, well-proven circuits for the IC design of active RC filters. We shall check the performance of these designed filters by computer simulation (e.g. PSpice). We shall then look at some special situations in communications systems that require (i), NOVEL TOPOLOGIES IN FILTER DESIGN and (ii), SPECIAL ATTENTION IN INTEGRATED-CIRCUIT DESIGN for higher frequency applications and higher bit-rate communications. At the end of the course, the student should be well prepared to embark on the design and performance evaluation of inductorless filters for the front end of typical and emerging communication systems on a chip. After completing you should be able to develop an understanding of:
George Moschytz is head of the School of Engineering at Bar-Ilan University, Israel.
Coming 2Q 2009: “bioMEMS/biosensors and Point-of-care Diagnostics” by Justin Williams, sponsored by the IEEE Engineering in Medicine and Biology Society This course will provide an introduction to the field of Micro-Electro-Mechanical Systems (MEMS) as it applies to biological applications (BioMEMS). After completing you should be able to develop an understanding of:
Justin Williams is an Assistant Professor in Biomedical Engineering and Neurological Surgery at the University of Wisconsin. He received his PhD from Arizona State in Bioengineering and did postdoctoral fellowships in Neuroengineering and Neurosurgery at the University of Michigan and the University of Wisconsin. His research interests involve BioMEMS device development for neurobiology, neuroscience and neurosurgical applications. He recently received the IEEE TNSRE 2007 outstanding paper award for his work on microfabricated implants for chronically recording electrical activity from single neurons in the cerebral cortex of behaving animals.
Coming 1Q 2009: “Cellular Wave Computers--Via Million Processing” by Tamas Roska, sponsored by the IEEE Circuits and Systems Society The cellular wave computer architecture, based on the CNN universal machine principle, has been implemented recently in many different physical forms. The mixed mode CMOS, the emulated digital (cell wise or as aggregated arrays), FPGA, DSP, as well as optical implementations are the main examples. In many cases, the sensory array is integrated as well. This course will begin with an introduction which will provide a historical overview, mind inspired and brain inspired computing models, the role of spatial address of a processor, new directions and products in computing The technology scenario. After completing you should be able to develop an understanding of:
Dr. Roska is a co-inventor of the CNN Universal Machine (with Leon O. Chua) and the analogic CNN Bionic Eye (with Frank S. Werblin and Leon O.Chua), US patents of UC Berkeley. During the last 15 years he has received two NSF grants, four ONR grants, two EU Grants and several Hungarian Grants. He has been a founding member of two spin/off companies, one in Berkeley and one in Budapest. Top
"Challenges Near the Limit of CMOS Scaling" by Yuan Taur, sponsored by the IEEE Electron Devices Society Beginning with a brief review of CMOS scaling trends, this course examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling. The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length. To extend CMOS scaling to the shortest channel length possible while still gaining significant performance benefit, an optimized, vertically and laterally nonuniform doping design (superhalo) is presented. It is projected that room-temperature CMOS will be scaled to 20-nm channel length with the superhalo profile. Low-temperature CMOS allows additional design space to further extend CMOS scaling to near 10 nm. After completing this course you should be able to develop an understanding of:
Yuan Taur is a professor in the Department of Electrical and Computer Engineering, University of California, San Diego.
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“Dealing with Issues in VLSI Interconnect Scaling” by Ron Ho, sponsored by the IEEE Solid-State Circuits Society Designers have recognized for many years that on-chip wires can limit system performance, and as technologies continue to scale, the problems posed by on-chip wires continue to worsen. This course discusses on-chip wires, how to model them, what their problems (and their advantages) are and some solutions. After completing you should be able to develop an understanding of:
Ron Ho is a Senior Research Scientist at Sun Microsystems Laboratories in Menlo Park, CA, where he worries about the future of wires. He received his Ph.D. in electrical engineering from Stanford University. From 1993 to 2003, he was at Intel in Santa Clara, CA, where he worked on processors ranging from the 80486 to the 3rd-generation Itanium. In 2003, he joined Sun Labs, where he is currently researching high-performance and low-energy communication technologies, both on a single chip and between two chips. In 2005, he was also a Lecturer at Stanford University, where he taught a graduate class on circuit design.
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"Design of Active-RC Filters for the Analog Front End (of Integrated Circuit System Chips)" by George S. Moschytz, sponsored by the IEEE Circuits & Systems Society The concept of the 'Analog Front End' (AFE), which is the interface to the real world in most IC-system chips, is first introduced. The course then focuses on active-RC filters which constitute an essential part of most AFEs. The formulation of filter specifications and the basic ideas associated with classical filter approximation theory are then briefly reviewed. Some key points of classical network theory, as needed for the understanding of inductorless filter design, are then briefly recalled. This is followed by some basic concepts of signal-flow graph theory, which permit the transition from transfer function (resulting from approximation theory) to circuit Topology. After the review of these introductory and basic concepts, the stage is set to consider some of the most important and established active-RC filter-design techniques. Examples are given for the conversion of classical LCR filter structures into inductorless active-RC filter circuits that are amenable to IC chip design. The examples are taken from typical modern communication systems. Finally, filters designed using the design techniques covered in the course are compared in terms of practical performance criteria such as thermal output noise, sensitivity to component tolerances, and tunablity. After completing you should be able to develop an understanding of:
George Moschytz is head of the School of Engineering at Bar-Ilan University, Israel.
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“Design of Phase Locked Loops” by Lama Dayaratna, sponsored by the IEEE Microwave Theory and Techniques Society The objective of this course is to provide a state of the art review of phase locked loop circuits and applications from a design and development perspective. Intended for RF and Microwave Engineers, the course details out the design and development of phase locked loop circuits. Topics include PLL basics, VCOs, phase detectors, open and close loop characterization, loop filter design, and phase noise concepts. Examples will be given to a variety of problems relevant to the design of phase locked loops. After completing you should be able to develop an understanding of:
Dr. Dayaratna holds a Ph.D. and has over 20-years of extensive experience in the theory and design of phase locked loop circuits with emphasis on low noise frequency synthesis techniques. Analyzed, designed, developed, and engineered Frequency Generation Architectures for communications payloads. Conceptualized, designed, built and led the first frequency generation architecture for LMCSS’ first mobile payload, which served as the cornerstone of LMCSS’s all subsequent Frequency Generation Units. As a Principal Engineer in the RF/Microwave Products area, Dr. Dayaratna is responsible for the design, development of RF/Microwave payload components such as receivers, transmitters, modulators, demodulators, synthesizers, and frequency generation equipment for all commercial satellite programs. Dr. Dayaratna also has over five years of teaching experience at graduate and undergraduate level.
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Coming 2Q 2009: “Design of Small Ultra-Wideband Antennas” by Zhi Ning Chen, sponsored by the IEEE Antennas and Propagation Society This is a hot Topic due to immediate demand from industry. However, the key design issues are often ignored, in particular by the students. In this course, these issues will be highlighted from an application point of view. The theoretical analysis is also given to help students understand the broadband radiation behavior well. The following is the abstract of the course. The research and development of ultra-wideband (UWB) technology has greatly spurred the design of small broadband antennas. The requirements for the UWB antennas include consistent impedance and radiation performance over an ultra-wide bandwidth of 3.1-4.8GHz/6-10.6GHz/3.1-10.6GHz. The miniaturization of the antennas becomes the most critical design challenges in commercial UWB systems such as high-speed wireless USB dongles. This course reviews the development of the small UWB antennas. The key design issues of the UWB antennas such as planar printed UWB antennas are highlighted. The new techniques to reduce the effect of ground plane on the antenna performance, further miniaturize antenna, co-design antenna with RF filters are elaborated. The latest applications of small printed antennas in wireless UWB systems are described in brief. After completing you should be able to develop an understanding of:
Dr. Chen received his BEng, MEng, PhD and DoE degrees all in Electrical Engineering from China and Japan. During 1988-1995, he worked as Lecturer and Associate Professor in Institute of Communications Engineering, China. Later he conducted his research in Southeast University, City University of Hong Kong, and University of Tsukuba, Japan (JSPS) as Associate Professor, Research Fellow, and Post-doctoral Fellow. In 2001 and 2004, he visited University of Tsukuba under JSPS Fellowship Program (senior level). In 2004, he worked at IBM T. J. Watson Research Center, USA as Academic Visitor. Since 1999, he has worked at Institute for Infocomm Research (I2R). His current appointments are Principal Scientist and Department Head for RF & Optical. He is concurrently holding Adjunct Professorships at Southeast University, Nanjing University, National University of Singapore, and Nanyang Technological University, Singapore. He is also Guest Professor at Shanghai Jiao Tong University.
"Design-Oriented Feedback Analysis" by David Middlebrook, sponsored by the IEEE Power Electronics Society This intermediate level course introduces the General Feedback Theorem (GFT), which is the culmination of design-oriented analysis approaches presented in five previous APEC Seminars. Feedback systems are usually designed with the familiar single-loop block diagram in mind. Various nonidealities, such as unavoidable minor loops and direct forward transmission, make the single-loop block diagram progressively less useful, especially at higher frequencies. The GFT defines a "natural" block diagram model that is identical in format to the single-loop model that is conventionally assumed, thus providing a desirable link between general feedback theory and a detailed circuit diagram analyzed in terms of factored pole-zero transfer functions. The GFT is illustrated on a potentially unstable Darlington emitter/source follower stage, and leads to design criteria that limit the maximum peaking regardless of the value of the load capacitance. Another example is a two-stage feedback amplifier having various nonidealities, including loading interactions at all points, direct forward transmission, and two minor loops. The GFT is computer friendly, and emphasis is on the numerical and graphical results obtained by use of an Intusoft ICAP/4 circuit simulator. After completing this course you should be able to develop an understanding of:
A distinguished international lecturer, Dr. R. David Middlebrook is Professor Emeritus of Electrical Engineering at the California Institute of Technology, and is particularly noted for presenting complex material in a simple, interesting, effective, and often entertaining manner, for which the Caltech student body has recognized him as an Outstanding Teacher.
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"Dynamically Adaptive Power Supply Circuits for Radio-Frequency (RF) Power Amplifier (PA) Applications" by Gabriel A. Rincón-Mora, sponsored by the IEEE Circuits and Systems Society, the IEEE Microwave Theory & Techniques Society, and the IEEE Solid State Circuits Society The role of Radio-Frequency (RF) Power Amplifiers (PAs) in today's and tomorrow's consumer and state-of-the-art electronics is crucial, catering to the stringent performance (i.e., linearity and output power) and real-estate (i.e., size) requirements of portable systems and the power limitations of battery-powered applications. Key to the success of any portable device is battery life (or runtime), and PAs can be a significant and detrimental load in this regard, especially because they capture a significant portion of the total power budget and they characteristically have poor power efficiencies. This course will address the advent of dynamically adaptive biasing schemes in PA applications to increase power efficiencies, which is generally done by essentially transforming and redefining the operating environment of the PA for maximum performance at optimum power levels, and consequently prolonging battery life. After completing this course you should be able to develop an understanding of:
Dr. Rincón-Mora received his B.S.E.E. from Florida International University (High Honors) in 1992 and M.S.E.E. and Ph.D. from Georgia Tech (Outstanding Ph.D. Graduate) in 1994 and 1996, respectively.
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"Effects of Reliability Mechanisms on VLSI Circuit Functionality" by Wayne Ellis, co-sponsored by the IEEE Electron Devices Society and IEEE Reliability Society This course provides examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to activate latent defects and screen out those chips that cannot meet product specifications for performance, power and operating margins. The advent of degraded VLSI circuit operating margins due to the activated defects as well as reliability mechanisms such as negative bias temperature instability (NBTI), hot carrier injection (HCI), and others will be discussed. How these failing circuits can then manifest themselves in observed product failures will also be discussed. After completing this course you should be able to develop an understanding of:
Wayne Ellis has worked from 1977 to the present at the IBM Microelectronics division labs in Essex Junction Vermont.
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Coming 1Q 2009: “Highly Integrated, Re-Configurable RF Receiver Front-Ends in Deep Sub-Micron CMOS” by Naveen Yanduru, sponsored by the IEEE Microwave Theory and Techniques Society Various RF bands, standards, modulation schemes, duplex mechanisms and signal bandwidths needed for the mobile terminal call for a highly adaptable and reconfigurable RF receiver. The biggest bottleneck in achieving this goal lies with the RF pre-select filter at the antenna, which is band specific and creates a bottleneck in being able to share the hardware. Solving this “multi-band” programmability is the biggest challenge in achieving a RF Receiver for software defined radio. A few of the possible architectures and their limitations are presented. However, designing a “multi-mode” RF receiver for a given RF band with highly reconfigurable performance is an achievable goal. A WCDMA/EDGE receiver without inter-stage SAW filter in 90nm digital CMOS is used as an example in illustrating the architecture, circuit and system considerations for such a receiver. After completing you should be able to develop an understanding of:
Naveen Yanduru serves as RF System and IC design manager and Member of Technical Staff in the Radio Design Organization at Texas Instruments, Inc. While at TI he has led several RF receiver design teams and projects for various cellular standards including GSM, W-CDMA, TDSCDMA, PDC and GPS. His research interests include multi-mode, multi-band receiver front-ends in deep submicron CMOS, quantifying the effect of AM blockers on RF receiver performance and design of on-chip RF filters. He has more than 10 years of experience in RF IC design, published over 16 papers in professional journals and international conferences. He is a Distinguished Lecturer of IEEE-CAS for the term 2007-2008.
“Interconnect Technology for 32 NM and Beyond” by Jeff Gambino, sponsored by the IEEE Electron Devices Society This course will provide an overview of advanced interconnect technologies, including dielectric materials, patterning, metallization, CMP, and packaging. New processes will be discussed, such as ultra-low K dielectrics, air-gap structures, low-damage patterning methods, thin barrier and seed layers, refractory metal capping layers, and novel CMP techniques. The effect of these processes on performance and reliability will be briefly described. After completing you should be able to develop an understanding of:
Jeff Gambino received the B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and the Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices. In 1992, he joined the DRAM development alliance at IBM’s Advanced Semiconductor Technology Center, Hopewell Junction, NY. In 1999, he joined IBM’s manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic and CMOS imager technology. He has published over 90 technical papers and holds over 100 patents.
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"Introduction to Developing Embedded Systems" by Kim Fowler, sponsored by the IEEE Instrumentation & Measurement Society This course introduces important issues in preparing, designing, and developing a product covering areas such as:
After completing this course you should be able to develop an understanding of:
Kim Fowler has spent over 22 years in the design, development, and project management of medical, military, and satellite equipment. He developed many different kinds of embedded systems at The Johns Hopkins University Applied Physics Laboratory; he currently manages technical programs there.
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"Introduction to Instrumentation" by Kim Fowler & John Schmalzel, sponsored by the IEEE Instrumentation & Measurement Society This course discusses how measurement is a key to life and explores where we use measurements. It defines instrumentation and measurement, reviews basic principles and covers areas such as:
Case studies detail car, LOX tank, submarine data acquisition system, medical device examples. This course also explores where instrumentation is found (e.g. laboratory, field instruments, car engine control, aircraft avionics and flight control, bridges, factories, houses, appliances) and discuss systems of instruments. It reviews sensor types, sizes and systems and covers basic instrumentation with a look at general configurations focused on areas such as inputs, conditioning and transformation, analog pre-processing, analog-to-digital converters (ADCs), outputs and basic processing. Review system configurations and the evolution of system designs are also discussed. After completing this course you should be able to develop and understanding of:
Kim Fowler has spent over 22 years in the design, development, and project management of medical, military, and satellite equipment. He developed many different kinds of embedded systems at The Johns Hopkins University Applied Physics Laboratory; he currently manages technical programs there. John Schmalzel founded the Electrical and Computer Engineering program at Rowan University where he is Professor and Chair.
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Coming 2Q 2009: “Introduction to Memristors” by Leon Chua sponsored by the IEEE Circuits and Systems Society This course will provide an overview of memristors. The course will explain what a memristor is, as well as what makes it the fourth circuit element. After completing you should be able to develop an understanding of:
Leon Chua is a professor from the University of California, Berkeley, He is known as a pioneer in nonlinear circuits, cellular neural networks, and chaos. His work in these areas has been recognized internationally through numerous major awards, including 7 USA patents, 11 honorary doctorates, and a foreign member of the European Academy Sciences (Academia Europea). He was honored with many major IEEE prizes, including the Browder J. Thompson Memorial Prize, the W. R. G. Baker Prize, the Frederick Emmons Award, the Neural Networks Pioneer Award, and the first IEEE Gustav Kirchhoff Award. He is also a Recipient of the Top 15 most cited authors Award in 2002 from all fields of engineering published during the 10-year period 1999 to 2001, from the Current Contents (ISI) database.
"Introduction to Statistical Variation and Techniques for Design Optimization" by Norman Rohrer sponsored by the IEEE Solid State Circuits Society Variability is a reality in nanometer semiconductor processes. This course will cover the sources of systematic and random variations of transistors and their surrounding interconnects. Included in the variability discussion will be withinchip variability, across-wafer variability, across-device variability, and device mismatch. The resulting impact upon an individual circuit’s functionality and timing will be explored. Analytical approaches will be shown for examining the variability’s impact upon leakage power, dynamic power, and circuit functionality of static and dynamic circuits, SRAM arrays, and PLLs. Techniques will include Monte-Carlo analysis, vector analysis, and statistical timing analysis. After completing this course you should be able to develop an understanding of:
Norman Rohrer is a Distinguished Engineer in the Power PC Microprocessor Group within the System-and-Technology Group of IBM, located in Essex Junction, VT.
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"Molecular Electronics Part 1: Potential and Applications" by Curt Richter, sponsored by the IEEE Electron Devices Society and the IEEE Reliability Society This course will begin by outlining approaching limits of conventional CMOS technology. New architectural requirements and paradigms for future nanoelectronics will be described. ‘Top-down’ and ‘bottom-up’ manufacturing paradigms, particularly self-assembly of organic monolayers will be discussed. Theoretical and experimental realizations of molecular-scale electronic switches will be described. This course will also show nanoscale memory and logic circuits built with these materials and methods and will discuss potential nanoscale chemical and biological sensors built with these materials and methods After completing this course you should be able to develop an understanding of:
Curt A. Richter, Ph.D. has worked in the Semiconductor Electronics Division of the National Institute of Standards and Technology, Gaithersburg, MD since 1993. He is currently Project Leader of the Nanoelectronic Device Metrology Project.
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"Molecular Electronics Part 2: Molecular Electronic Device Fabrication and Characterization " by Duncan Stewart, sponsored by the IEEE Electron Devices Society and the IEEE Reliability Society This course will begin by discussing the advantages of molecular electronic devices and present experimental proof of concepts. The formation of molecular junctions, the central component of molecular electronic devices will be described as well as the design and fabrication approaches for some of the most successful molecular electronic device prototypes. This course will also present electrical characterization approaches and challenges and discuss non-device based electrical screening approaches. Finally, the current status and outlook for molecular electronic devices will be presented. After completing this course you should be able to develop an understanding of:
Duncan R. Stewart, Ph.D. first studied physics and electrical engineering at the University of Toronto, Canada, earning his BASc in 1992. He moved to Stanford University to complete a PhD in Applied Physics in 1999, where he studied nanoscale electron transport in high-mobility GaAs quantum dots, particularly many-body effects in the excited state spectra of these ‘artificial atoms’.
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Coming 2Q 2009: “Multigigabit Wireless: CMOS & FR-4 at 60 GHz” by Joy Laskar sponsored by the IEEE Microwave Theory and Techniques Society This course will present an overview of mmW Digital CMOS Radio technology building blocks and system applications. After completing you should be able to develop an understanding of:
Dr. Joy Laskar received the B.S. degree (Computer Engineering with Math/Physics Minors, summa cum laude) from Clemson University in 1985. He received the M.S. and the Ph.D. degrees in Electrical Engineering from the University of Illinois at Urbana-Champaign in 1989 and 1991 respectively. Prior to joining Georgia Tech in 1995, Dr. Laskar was a visiting professor at the University of Illinois at Urbana-Champaign and an assistant professor at the University of Hawaii at Manoa. At Georgia Tech he holds the Schlumberger Chair in Microelectronics in the School of Electrical and Computer Engineering. He is also Founder and Director of the Georgia Electronic Design Center, and he heads a research group of 50 members (graduate students, research staff and administration) with a focus on integration of high-frequency mixed-signal electronics for next-generation wireless and wire line systems. Between 1995 through fall 2007 Professor Laskar has graduated 34 Ph.D. students. He has authored or co-authored more than 480 papers, several book chapters and three books (with another book in development). He gave numerous invited talks and has more than 40 patents issued or pending.
Coming 2Q 2009: “Nanophotonics: Physics and Techniques” by Axel Scherer sponsored by the IEEE Photonics Society This course will start with an introduction to photonic crystals, photonic crystal nanocavities and lasers fabricated in thin semiconductor slabs containing quantum wells. The characteristics and applications of ultrasmall lasers will be described for spectroscopy, and the opportunities for optical nanocavities in quantum information processing will be reviewed. This will be followed by a description of the integration opportunities of photonic crystal cavities with vertical cavity surface emitting and microdisk lasers. The attributes of high Q micro-toroid cavities will be compared with ultra-small medium Q microfabricated nanocavities. The course will also cover CMOS silicon photonics for data communications applications. Moreover, the opportunities of integrating photonics with fluidics in the field of opto-fluidics will be introduced. Finally, a comparison will be made between photonic crystal geometries and conventional high index optics, and surface plasmon optics. Plasmon enhanced light emitters and waveguides will be introduced, and their applications in highly efficient solid state light emitters will be summarized. After completing you should be able to develop an understanding of:
Axel Scherer is the Bernard A. Neches Professor of Electrical Engineering, Applied Physics and Physics at Caltech. He received his PhD in 1985, and after working in the Microstructures Research Group at Bellcore, moved to Caltech in 1993. Scherer’s group now works on micro- and nano-fabrication of optical, magnetic and fluidic devices. He has authored and co-authored over 250 publications and holds 50 patents in the field of optoelectronic and microfluidic nanostructures, as well as new nanofabrication techniques. Scherer specializes in, and has built a state-of-the-art laboratory for advanced high-resolution lithography and anisotropic ion etching at Caltech. He has fabricated microcavity lasers, such as vertical cavity surface emitting lasers (VCSELs) and photonic crystal lasers. Presently, his group works on microfabrication of microfluidic chips, single-domain nanomagnets, photonic crystal waveguides and lasers, and the development of novel lithography techniques.
"Nanotechnology 101 Part 1" by H.-S. Philip Wong, sponsored by the IEEE Solid-State Circuits Society This course provides an introduction to the emerging opportunities in novel nanoscale devices and fabrication techniques, with particular emphasis on the implications for circuit and system designers. Topics covered include: fundamentals of device physics and materials science at the nanoscale, and the ITRS Emerging Research Devices (memory & logic). After completing this course you should be able to develop an understanding of:
H.-S. Philip Wong joined the IBM T. J. Watson Research Center, Yorktown Heights, New York, in 1988. In September, 2004, he joined Stanford University as Professor of Electrical Engineering.
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"Nanotechnology 101 Part 2" by H.-S. Philip Wong, sponsored by the IEEE Solid-State Circuits Society This course expands on the materials presented in "Nanotechnology 101 Part 1," and delves further to cover Topics such as: nanotubes, nanowires, and nanoparticles, molecular devices, nanofabrication techniques and their impact on device layout. An assessment of the level of maturity for the proposed devices will be given. After completing this course you should be able to develop an understanding of:
H.-S. Philip Wong joined the IBM T. J. Watson Research Center, Yorktown Heights, New York, in 1988. In September, 2004, he joined Stanford University as Professor of Electrical Engineering.
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"Organic Field Effect Transistors" by Ioannis (John) Kymissis, sponsored by the IEEE Solid State Circuits Society The course will explain the theory underlying OFET operation, discuss practical fabrication strategies in use and underdevelopment, and discuss characterization and simulation of these devices, and some simple circuit implications of their performance strengths and limitations. After completing this course you should be able to develop an understanding of:
Ioannis (John) Kymissis is currently a post-doc at MIT and senior consulting engineer at an OLED startup. He is starting as an assistant professorship at Columbia University in July 2006.
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"Power Electronics System Thermal Design: Linear Superposition" by Roger Stout, sponsored by the IEEE Power Electronics Society This course will introduce an overall approach to electronics system thermal characterization and design, based on the principle of linear superposition. It will also dispel common misunderstandings and misuses of conventional thermal characterization data, in particular, theta-JA, on semiconductor device packages. After completing this course you should be able to develop an understanding of:
Roger Stout received his BSE in Mechanical Engineering at ASU in 1977, and went on as a Hughes Fellow to earn his MSME at the California Institute of Technology in 1979. In 1999, Roger became a charter employee of ON Semiconductor and resident thermal characterization expert. He currently carries the job title of Senior Research Scientist, at ON Semiconductor. Roger holds six patents and has been a registered Professional Engineer in the state of Arizona since 1983.
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"Power Electronics System Thermal Design: Thermal Runaway" by Roger Stout, sponsored by the IEEE Power Electronics Society This course will provide an in-depth presentation of specific and highly non-linear thermal failure mechanisms (thermal runaway). The course will discuss how it arises and how it may be analyzed. The focus will be within the particular context of power semiconductor devices, but it should also become evident how the concept may be applied more generally. After completing this course you should be able to develop an understanding of:
Roger Stout received his BSE in Mechanical Engineering at ASU in 1977, and went on as a Hughes Fellow to earn his MSME at the California Institute of Technology in 1979. In 1999, Roger became a charter employee of ON Semiconductor and resident thermal characterization expert. He currently carries the job title of Senior Research Scientist, at ON Semiconductor. Roger holds six patents and has been a registered Professional Engineer in the state of Arizona since 1983.
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"Practical Phase-Locked Loop Design" by Dennis Fischette, sponsored by the IEEE Solid-State Circuits Society This course provides a practical introduction to PLL design for clock synthesis. The twin goals of the course are:
This course includes basic feedback loop theory and common circuit implementations, with emphasis on typical problem spots. The course also focuses on design for test and debug, an important but often overlooked Topic. After completing this course you should be able to develop an understanding of:
Dennis Fischette has been responsible for phase-locked loops, delay-locked loops, digital clock circuitry, high-speed I/O receivers, and clock/data recovery at Advanced Micro Devices since 2000.
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"Process Technology" by Scott Crowder, sponsored by the IEEE Electron Devices Society This course will discuss the requirements and transistor design issues in current and future low power technologies. After reviewing the tradeoffs between low standby and low active power, the methods for and required future innovations in low power process and transistor design will be discussed. After completing this course you should be able to develop an understanding of:
Scott Crowder received a B.S./B.A. degree in Electrical Engineering and International Relations from Brown University in 1990. He pursued a graduate school education at Stanford University; receiving a M.S. degree in Electrical Engineering, a M.A. degree in Economics, and a Ph.D. degrees in Electrical Engineering in 1990, 1994, and 1995 respectively. In 1995, he joined IBM’s Semiconductor Research & Development Center. He was the technical lead on the development of IBM’s logic based embedded DRAM technology and 180nm high-performance logic technology. He has since managed various organizations within SRDC involving transistor design, macro design, compact models, data prep, unit process and process integration; most recently as Director of 90/45nm Technology Development. His organization was responsible for development of high-performance SOI and foundry bulk technologies, IBM’s embedded DRAM process, and macro designs for embedded DRAM and electronic fuse technologies. He has also served as the executive responsible for the process technology alliance of Infineon, Chartered, Samsung and IBM. Scott is now part of the Corporate Strategy organization at IBM. He holds 6 U.S. patents and has authored 16 technical journal publications.
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Coming 2Q 2009: “Recent Advances in LDMOS Technology” by Wayne Burger, sponsored by the IEEE Microwave Theory and Techniques Society This course begins by providing a review of recent advances in RF-LDMOS device technology (i.e. high power plastic packaging, higher efficiency, higher frequency capability, high power RFICs, 50V RF-LDMOS, etc.). Next, the course will provide a comparison of various figures of merit of 28V and 50V RF-LDMOS with GaN, an emerging RF power technology that is attractive from several perspectives as an RF power device technology. After completing you should be able to develop an understanding of:
Wayne Burger graduated from MIT with a Ph.D. in Electrical Engineering in 1987, with his thesis work focusing on the deposition and characterization of low temperature silicon epitaxial films. After working on BiCMOS SRAM's at National Semiconductor for two years, he joined Motorola's Semiconductor Product Sector (which later became Freescale Semiconductor) in 1990. Early projects at Motorola include 0.60um CMOS and 0.35um BiCMOS development. Dr. Burger has been manager of the RF-LDMOS Device Development team at Freescale Semiconductor since 1994.
Coming 2Q 2009: "Silicon Lasers and Light Emitters" by John Bowers, sponsored by the IEEE Photonics Society Silicon photonics is an exciting research field with the promise of revolutionizing communications by enabling highly integrated electronic and photonic circuits. This course will review the research on light emission in silicon and silicon photonic ICs. A novel, wafer scale approach that uses a CMOS compatible bonding process to bond III-V layers onto a SOI wafer to enable the fabrication of silicon lasers will be discussed. After completing you should be able to develop an understanding of:
John Bowers is a professor in the Department of Electrical Engineering and in the Technology management Program at the University of California, Santa Barbara. He is also CTO and cofounder of Client Networks.
"Silicon-Germanium (SiGe) IC Devices & Technology" by John D. Cressler, sponsored by the IEEE Electron Devices Society The silicon-germanium heterojunction bipolar transistor (SiGe HBT) is the first practical bandgap-engineered device to be realized in silicon. SiGe HBT technology combines transistor performance competitive with III-V technologies such as GaAs and InP with the processing maturity, integration levels, yield, and hence cost commonly associated with conventional Si CMOS fabrication. Since the first demonstration of a functional transistor in 1987, SiGe HBT technology has emerged from the research laboratory, entered manufacturing on 200 mm wafers, and is currently making in-roads in the commercial electronics market in the US, Europe, and the Far East. First-generation SiGe HBTs can deliver: fT in excess of 50 GHz, fmax in excess of 70 GHz, minimum noise figure below 0.5 dB at 2.0 GHz, linearity efficiency (OIP3/Pdc) above 10, 1/f noise corner frequencies below 1 kHz, operation at cryogenic temperatures, excellent radiation hardness, as well as yield, reliability and cost comparable to Si. Aggressively-scaled SiGe HBTs are capable of achieving greater than 200 GHz transistor-level performance, and thus are expected to enable Si-based solutions for >40 GB/sec data links and emerging RF, microwave, and even mm-wave systems. A host of record-setting digital, analog, RF, and microwave circuits have been demonstrated using SiGe HBTs, and the combination of SiGe HBTs with advanced Si CMOS to form a SiGe HBT BiCMOS technology represents a unique opportunity for Si-based system-on-a-chip solutions for emerging wireless and wireline applications. This course will provide a comprehensive review of the state-of-the-art in SiGe HBTs and assess its potential for current and future wireless and wireline applications. After completing this course you should be able to develop an understanding of:
John D. Cressler is currently Professor of electrical and computer engineering at the Georgia Institute of Technology (Georgia Tech).
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"The Principles of Delta-Sigma Data Converters" by Gabor Temes, sponsored by the IEEE Circuits and Systems Society from the IEEE International Conference on Electro/Information Technology This course provides a clear understanding of the principles of delta-sigma converter operation—analog to digital and digital to analog. It introduces the best computer-aided analysis and design techniques available. The course uses simplified methods to illustrate complicated concepts such as spectral estimation and switched noise. After completing this course you should be able to develop an understanding of:
Gabor Temes received his undergraduate education in Hungary, and his PhD from the University of Ottawa, Canada, in 1961. He held industrial positions at Bell-Northern Research and Ampex Corp., and academic ones at Stanford University and UCLA. He is currently Professor in the School of Electrical Engineering and Computer Science at Oregon State University. He is a Life Fellow of the IEEE, and a recipient of the Graduate Education Award as well as the Gustav Robert Kirchhoff award of the IEEE.
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"Tunable Semiconductor Lasers" by Jens Buus, sponsored by the IEEE Photonics Society This course describes the state-of-the-art of tunable lasers, tunable laser technologies and control of tunable lasers. It also includes a brief introduction to the basics of semiconductor lasers, as well as background on DFB lasers, in particular how a grating works as a wavelength selective element in DFB and DBR lasers. Tuning mechanisms and tuning properties will be described, and the operation of modified structures with extended tuning range will be explained, including sampled gratings and super structure gratings. The properties of codirectional couplers and the use of these in tunable lasers will be discussed. Devices such as external cavity lasers, wavelength selectable lasers, and tunable VCSELs, will also be described. Throughout the course numerous examples of laser structures from the recent technical literature will be presented. Practical issues such as characterization, operation, and control of tunable lasers, as well as switching speed and reliability, will be included. After completing this course you should be able to develop an understanding of:
Jens Buus is an electrical engineer (MSc in electrophysics). He graduated from the Technical University of Denmark (DTU). In addition he holds Lic. techn. (PhD) and Dr. techn. (DSc) degrees from this University. Since January 1993 he has been a self employed consultant (Gayton Photonics Ltd). He has worked as project manager of 6 international research projects under the European RACE, ACTS and IST programmes.
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"Understanding On-Chip Transmission Lines Part 1" by Alina Deutsch sponsored by IEEE Educational Activities This course reviews the present-day on-chip wiring design practices and the special characteristics of on-chip lossy transmission lines. The deficiencies of present-day RC-circuit-representation-based designs and tools are highlighted through relevant examples. Guidelines are given for how to use controlled transmission line structures and design practices are discussed for best optimizing the wiring structure and design methodologies to circumvent the negative effects and best utilize the transmission line properties in the framework of improved technological advances. CAD tool development needs are explained for wire-aware chip architecture and for migrating to performance-driven routers and layout with R(f)L(f)C interconnect representation. The large, integrated chips that are including major portions of the overall system are inheriting all the problems that package designers have faced for many years. It is explained how the system-on-chip concept needs to adopt and adapt the tools, understanding, and practices used for designing chip-to-chip interconnections. After completing this course you should be able to develop an understanding of:
Alina Deutsch (Fellow IEEE) received the B.S. and M.S. degrees in Electrical Engineering from Columbia University, NY, and Syracuse University, Syracuse, in 1971 and 1976, respectively. She has been at IBM since 1971 and has worked in several areas, including testing of semiconductor and magnetic bubble memory devices.
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"Understanding On-Chip Transmission Lines Part 2" by Alina Deutsch sponsored by IEEE Educational Activities This course delves further into the present-day on-chip wiring design practices and the special characteristics of on-chip lossy transmission lines. A new technique is described for reducing computational complexity and improving accuracy of combined power distribution and interconnect noise prediction for wide, on-chip data-buses. The methodology uses lossy transmission-line power-blocks with frequency-dependent properties and the interaction between delta-I noise, common-mode noise, and crosstalk and their effect on timing is illustrated with simulations using representative driver and receiver circuits and on-chip interconnections. After completing this course you should be able to develop an understanding of:
Alina Deutsch (Fellow IEEE) received the B.S. and M.S. degrees in Electrical Engineering from Columbia University, NY, and Syracuse University, Syracuse, in 1971 and 1976, respectively. She has been at IBM since 1971 and has worked in several areas, including testing of semiconductor and magnetic bubble memory devices.
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"Wireless-LAN Radio Design" by Arya Behzad, sponsored by the IEEE Solid-State Circuits Society As one of the few rising stars of the semiconductor industry, WLAN design is engaging more and more engineers and companies. Essential to the overall system design, is the radio design. This course will introduce the various flavors of the 802.11 WLAN PHY standards (A/B/G) and describe their specifications and impact on the radio design. The possible choices for the radio architecture (direct-conversion, low-IF, super-heterodyne) are examined and their impact on the transistor-level design will be studied. The impact of the radio architecture on die size, system cost, and power consumption is evaluated. The effect of certain analog/RF impairments on the overall system performance is also described, along with the choice of process technology on the radio architecture. Some analog/digital/mixed-mode calibration techniques for improving system performance and chip yield are presented. Finally, a specific case-study is examined in detail. Several key building blocks are discussed at the transistor-level. Most of the transistor-level circuits will be of the CMOS type. The course will present the theory behind the discussed Topics in some detail. However the emphasis of the course is on practical aspects of design for wireless LAN radios. After completing this course you should be able to develop an understanding of:
Arya Behzad is Product Line Manager for all WLAN radios and Director of Engineering at Broadcom Corporation. He is also a Broadcom Distinguished Engineer.
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