James H. Stathis’ and Ernest Yue Wu’s expertise of gate dielectric reliability has permitted circuit designers to push transistor performance to the limit by continuing dielectric scaling while maintaining operation voltage sufficient to deliver high drive current integral to today’s smaller yet more powerful devices. Their work has provided the ability to accurately predict the oxide lifetime at use conditions from accelerated stress data at elevated voltages, which has been essential as oxide thickness has scaled from ~10 nm to ~1 nm. Stathis challenged the semiconductor roadmap assumption that the constant-field scaling of gate oxides could continue without impacting transistor reliability. This motivated the industry to start looking for alternative (high-k) dielectrics. He then helped discover “progressive breakdown” and showed how to confidently achieve better reliability margins. Wu developed a power-law model for voltage dependence of gate oxide breakdown that profoundly changed the landscape for semiconductor scaling. Building on the progressive breakdown concept, he created a failure-current-based methodology that led to a comprehensive understanding of transistor failure.
An IEEE Fellow, Stathis is a principal research staff member with IBM Research, Yorktown Heights, New York, USA.
An IEEE Fellow, Wu is a senior technical staff member with IBM Research, Essex Junction, Vermont, USA.
The combined efforts of Daniel C. Edelstein, Alfred Grill, and C-K Hu in making the benefits of copper (Cu) interconnect technologies a feasible reality forever changed semiconductor manufacturing and allowed the continued scaling of microelectronics. Their pioneering work overcame the manufacturing and reliability challenges of introducing a new materials process to replace aluminum interconnects. Edelstein described a qualified and commercial Cu interconnect technology. His dual damascene structure yielded unique microstructures in electroplated Cu nanowires, making it possible to study effects of nanoscale surfaces and interfaces on electron resistivity and mass transport in Cu lines. Grill’s development of silicon-carbon-oxygen-hydrogen (SiCOH) dielectrics provided a unique class of low-k dielectrics with strong chemical bonds, offering a distinct molecular structure that strengthened the thermomechanical properties of porous low-k materials. Hu’s work on electromigration of Cu interconnects provided insights to understanding the basic scaling law for predicting the degradation of electromigration lifetime and development of new materials for future technology nodes.
An IEEE Senior member, Edelstein is an IBM Fellow at the IBM T.J. Watson Research Center, Yorktown Heights, NY, USA.
Grill is an IBM Fellow Emeritus at the IBM T.J. Watson Research Center, Yorktown Heights, NY, USA.
Hu is a research staff member at the IBM T.J. Watson Research Center, Yorktown Heights, NY, USA.
One of the founders of modern Technology Computer Aided Design (TCAD), Siegfried Selberherr has provided modeling and software development tools invaluable to the continued miniaturization of semiconductor devices. TCAD involves the use of computer simulation to develop and optimize semiconductor processing technologies. Selberherr developed MINIMOS for two-dimensional predictive simulation of the electrical characteristics of miniaturized devices to understand and control the short-channel effects and doping profiles encountered as device sizes shrink. MINIMOS was later enhanced for three-dimensional simulation to address energy transport and interface physics. He also created the ZOMBIE and PROMIS simulators, which incorporated mesh generation and programming interfaces. Selberherr then developed the Vienna Integrated System for TCAD Applications (VISTA) to combine both process and device simulation tools in a common framework. An IEEE Fellow, Selberherr is a professor with the Institute for Microelectronics at the Technische Universität Wien, Vienna, Austria.
Guido Groeseneken has been dedicated to tackling the most critical reliability issues facing the continued scaling of semiconductors to help enable today’s smaller, more powerful, and more efficient electronics. He developed the charge pumping technique, which quickly became a powerful method for the characterization of metal-oxide semiconductor field-effect transistor (MOSFET) devices. He used the technique to better understand hot-carrier injection, which allowed the semiconductor industry to optimize technologies to achieve longer lifetimes. He and his team developed the percolation model to explain time-dependent dielectric breakdown, identified transient charging effects as a limitation to the commercialization of high-k dielectrics, and developed a measurement method to quantify these effects. His work has facilitated the development of very thin, high-k materials important to the further miniaturization of micro- and nano electronic devices. An IEEE Fellow, Groeseneken is a Research Fellow with IMEC and professor with the KU Leuven, Belgium.
Akira Toriumi’s pioneering contributions to understanding advanced gate dielectrics and device physics are driving the continued miniaturization of components needed for current and future electronic devices. His early work on random dopant fluctuation-induced threshold voltage variation and its effect on device reliability addressed an important source of variation facing device design when trying to further scale power supply voltage. In the area of high-k silicon dielectrics, Toriumi demonstrated some of the thinnest reliable dielectrics to date to enable high-k gate stacks. He has also pioneered the investigation of using germanium as an alternative channel material for high-performance CMOS, which will be critical to providing the reduced power supply voltages needed for even smaller future technology generations.
An IEEE Senior member, Toriumi is a professor with the Department of Materials Engineering at the University of Tokyo, Tokyo, Japan.
Hiroshi Iwai’s dedication to pushing the boundaries of integrated circuit scaling broke perceived barriers to enable the continued miniaturization of electronic devices providing higher performance with lower power that are integral to today’s mobile electronics. When industry forecasted that complimentary metal-oxide-semiconductor (CMOS) scaling wouldn’t go below 1 micrometer due to current leakage and lithography issues, Prof. Iwai provided solutions demonstrating that 25-nanometer (nm) scaling was possible. Among his many innovations, he developed technologies for shallow junctions and optical lithography to allow fabrication of 40-nm gate-length CMOS transistors. He also devised techniques for growing ultra-thin silicon oxide films to overcome leakage issues when using extremely small gate lengths. Overall, Prof. Iwai’s contributions demonstrated to industry that sub-50-nm CMOS scaling could be achieved.
An IEEE Life Fellow, Prof. Iwai is a professor with the Tokyo Institute of Technology, Yokohama, Kangawa, Japan.
For over 30 years, Martin A. van den Brink’s vision has driven advances in optical lithography methods that enable smaller, faster, and more energy-efficient chips. Optical lithography, a microfabrication process in which light-sensitive chemicals are used to transfer circuit patterns onto chip wafers, is the technology of choice for mass production of integrated circuits and a key enabler of the continued miniaturization of chips. Under Dr. van den Brink’s leadership, innovations including alignment modules, focusing and leveling methods, and staging concepts have continued to drive the industry forward, providing nanometer-scale accuracy. The TWINSCAN exposure platform, 193-nm immersion lithography scanners, and extreme ultraviolet scanners, have allowed printing at smaller and smaller dimensions every year. His work has truly shaped the optical lithography field.
Dr. Van den Brink is President of ASML, Veldhoven, The Netherlands.
A world-renowned expert on semiconductor device physics and modeling, Giorgio Baccarani’s contributions to scaling theory have been pivotal to the continued miniaturization of electronic devices from micrometer to nanometer scales. Baccarani’s generalized scaling theory published in 1984 has provided the theoretical foundations to help engineers understand earlier scaling rules for electronic components. He has provided the tools needed to predict, interpret, and understand the characteristics of miniaturized MOS transistors. Baccarani provided one of the first transistor models where surface potential is accurately calculated using an iterative procedure. This work is considered the forerunner of today’s PSP (Penn State Philips) model for simulating behavior of future MOS transistors. He also developed physical models for numerical device simulation that have been incorporated into commercial technology computer-aided design (TCAD) tools for modeling semiconductor fabrication. Baccarani also created numerical modeling techniques of electron devices in two and three dimensions.
An IEEE Life Fellow, Baccarani is a professor with the University of Bologna, Italy.
As the architects of Intel Corporation’s lithography technology and strategy, Yan Borodovsky and Sam Sivakumar have advanced the art and science of lithographic patterning and kept Intel at the forefront of continued miniaturization of electronic devices. Mr. Borodovsky and Mr. Sivakumar were instrumental in developing the first 45-nm lithography process for Intel in 2007. By deploying a regular layout of unidirectional lines, they were able to extend 193-nm dry lithography for use on Intel’s 45-nm generation. Mr. Borodovsky and Mr. Sivakumar then developed a robust patterning process using immersion lithography for Intel’s 32-nm generation. Their contributions again enabled Intel to move this technology into production ahead of the industry. Mr. Borodovsky and Mr. Sivakumar have also made innovative contributions to developing new resolution enhancement technology techniques, including pixelated phase masks, chromeless phase-shift masks, and inverse lithography. These techniques allow the extension of immersion lithography to the 22-nm node, which ushered in the era of Tri-Gate transistors with the start of mass production in 2011.
An Intel Senior Fellow, Yan Borodovsky is currently director of advanced lithography with Intel Corporation, Hillsboro, Ore., where he has worked since 1987.
An IEEE Member and Intel Fellow, Sam Sivakumar is currently director of lithography with Intel Corporation, Hillsboro, Ore., where he has worked since 1990.
The insight provided by Massimo V. Fischetti, David J. Frank, and Steven E. Laux in understanding the physical effects that occur in electronic devices at small dimensions has been key to silicon technology evolving at a rapid pace. Their collective work on the development and application of modeling and simulation tools over the past 20 years have provided guidance during the early stages of the design cycle, reducing R&D costs for future nanotechnology. Drs. Fischetti and Laux developed the full-band Monte Carlo simulation program DAMOCLES, which shed light on the physics governing electron transport in semiconductor devices. The tool is considered the gold standard for device modeling with its ability to capture realistic physical properties in small silicon transistors, explaining key phenomena and suggesting new directions for research. Drs. Fischetti, Frank, and Laux demonstrated 30-nn gate lengths in silicon transistors in 1992, at a time when industry thought it difficult to scale to transistor gate lengths below 100-nm. With impact still being felt today, their work sparked worldwide interest in pursuing the double-gate transistor structure as the ultimately scaled silicon transistor.
Dr. Fischetti is the Texas Instruments Distinguished Chair in Nanoelectronics with the Materials Science and Engineering Department at the University of Texas at Dallas.
An IEEE Fellow, Dr. Frank is a research staff member at the IBM T.J. Watson Research Center, Yorktown Heights, NY, USA.
An IEEE Fellow, Dr. Laux is a research staff member at the IBM T.J. Watson Research Center.
Burn J. Lin is recognized as a technical leader in the semiconductor manufacturing industry and most responsible for 193-nm immersion lithography. In 2002, Dr. Lin proposed immersion lithography, which is a resolution-enhancement process that replaces the air gap between the lens and the wafer surface with a liquid medium, such as purified water. Through Dr. Lin’s perseverance in convincing the industry that a change was needed, immersion lithography was adopted, and manufacturing of 45-nm feature sizes and smaller have become possible.
He has continued the cause for immersion lithography with groundbreaking papers that have mapped out scaling laws for super-high numerical aperture immersion optics, and he has led the development of defect-reduction methods to address concerns regarding the technology. As a result, immersion lithography has quickly become a manufacturing technology in just a few years.
An IEEE Life Fellow, Dr. Lin is currently the senior director of the Nanopatterning Technology Division at TSMC, Ltd., the world’s largest silicon foundry.
Michel Bruel created and patented the Smart Cut process, a method of producing high volumes of semiconductors in ultra-thin, Silicon on Insulator (SOI) wafers. Smart Cut technology makes it possible to cut a very thin layer of single crystal semiconductor from a bulk semiconductor wafer, and transfer it to any kind of other substrate. This thinner and smaller chip fabrication, increased the speed of the processor and lowered the power consumption, thereby making SOIs attractive to a wider variety of applications, including portable electronics, laptop computers, smart power devices and navigational aids. Early in his career, Dr. Bruel headed the Ion Implantation group at Commissariat a l'Energie Atomique - Laboratoire d'Electronique et de Traitement de I'lnformation (LETI) in Grenoble, France, and is currently LETI Scientific Advisor
Sandip Tiwari, the Charles N. Mellowes Professor of Engineering at Cornell University in Ithaca, N.Y., has made seminal contributions to the field of nanotechnology, resulting in greatly increased storage capacities for compact devices used in mobile communications, computing and other applications.
Over his career, he has repeatedly broken new ground in areas spanning heterostructures, quantum confinement and nano-devices. Dr. Tiwari’s early research led to several technologies currently in use in compound semiconductors and other device phenomena including electron injection processes in coupled confined systems and frequency limitations of quantum-wire lasers due to gain compression. His research with semiconductors, nonlinearity, coupling across scales and adaptation also helped advance the fields of electronics and photonics.
An IEEE Fellow, he received the 1991 Young Scientist Award from the Institute of Physics and the 2003 Distinguished Alumnus Award from the Indian Institute of Technology.
Dr. Susumu Namba, Professor Emeritus at Osaka University and the Nagasaki Institute of Applied Science, and the Honorary Scientist of RIKEN, the Institute of Physical and Chemical Research, has pioneered many innovations in beam-based micro fabrication for micro and optical electronic devices.
He developed the first electron beam micro fabrication technology, leading to electron beam lithography for semiconductor manufacturing. He developed the ion implantation technology, and made an academic basis for the technique. His groundbreaking techniques for submicron control of doping profiles and the development of the ion beam etching technique are credited with bringing the semiconductor into the submicron era.
His work with focused ion beam systems with liquid-metal ion sources has had a profound influence on the semiconductor industry, creating new, greatly improved methods for failure analysis, circuit repair and modification, in situ processing and lithographic mask repair.
His pioneering work on the modulation of light with electro-optic effects in ’50s led to the present light communication technology. Besides, he made pioneering works on the excimer laser lithography and synclotron (SOR) lithography.
During his 40 year tenure as a professor in the Electrical Engineering and Computer Science Department at the University of California at Berkeley, Dr. William Oldham became a recognized leader in the field of integrated circuit (IC) miniaturization technology. He pioneered the definition and development of practical simulators for micropatterning, including deposition, etching and lithography. His invention of sealed-interface local oxidation significantly reduced the formation of bird's beak in the local oxidation process, improving device performance. His recent work on maskless lithography is expected to bring improvements in chip development and the customized manufacture of specialized chips in limited quantities.
Dr. Oldham is professor emeritus and Robert S. Pepper Distinguished Professor of Electrical Engineering at the university. An IEEE Fellow, he has served on the IEEE Electron Devices Society Administrative Committee and is a member of the U.S. National Academy of Engineering.
Dr. Stephen Y. Chou's pioneer research on a broad variety of nanotechnologies and nanodevices has helped to shape new paths in the fields of nanofabrication, nanoscale electronics, optoelectronics, magnetics and materials. His graduate work used X-ray lithography to scale MOSFETs to the 60 nm range, and since 1984, he has demonstrated very small MOSFETs, single electron transistors, nanophotonic devices, and nanomagnetic devices. His development of nanoimprint lithography (NIL) since 1994 gave rise to a revolutionary method that allows 10 nm patterning over large areas with high throughput and low cost, providing a key enabling tool for nanotechnology. An IEEE and Packard Fellow, Dr. Chou has published more than 280 papers and holds eight U.S. patents. His work has been cited over 3000 times by other scientific journal papers. Since 1997, he has been the Joseph C. Elgin Professor of Electrical Engineering and head of the NanoStructure Laboratory at Princeton University, Princeton, New Jersey.
Dr. Mark Lundstrom’s groundbreaking effort in scattering models for transistors has provided key insights into nano-scale transistor physics and performance limits. His work with Dr. Supriyo Datta is noted by the challenges they address and by their ability to communicate their ideas to the broader electron device community. He is known for his pioneering studies of carrier transport in nonoscale transistors, his work on scaling limits of transistors and his scattering matrix approach to semiclassical carrier transport. His book, Fundamentals of Carrier Transport, uniquely describes techniques for carrier transport in systems as different as semiconductor junctions and ion diffusion structures. A Fellow of both the IEEE and the American Physical Society, Dr. Lundstrom has published over 200 conference and journal papers. His awards include the Frederick Emmons Terman Award from the American Society of Engineering Education. He is a professor at Purdue University.
Dr. Supriyo Datta is a leading figure in the modeling and understanding of nano-scale electronic conduction. With Mark Lundstrom, he has pioneered electronic-flow prediction in ultrasmall devices. His early work laid the foundation for quantum-transport simulation tools based on the non-equilibrium Greens function formalism. He also is well known for his seminal contributions to such emerging fields as spintronics and molecular electronics. A Fellow of the IEEE, the American Physical Society and the Institute of Physics, his many honors include the National Science Foundation Presidential Young Investigator Award and the D.D. Ewing Teaching Award from the Purdue University School of Engineering. Dr. Datta is the Thomas Duncan Distinguished Professor of Electrical and Computer Engineering at Purdue University.