Without Digh Hisamoto’s development of the three-dimensional (3D) double-gate metal-oxide-silicon field effect transistor (MOSFET) in 1989, many of today’s advanced logic products likely would not exist. With conventional planar MOSFET scaling becoming more difficult due to challenges including short-channel effects, Hisamoto’s DELTA 3D MOSFET was instrumental in allowing miniaturization to continue. He was the first to recognize that it was possible to solve process issues if the channel was formed in vertical “fin” surfaces. His 3D MOSFET featured strong immunity to short-channel effects, high mobility, and reduced threshold voltage variation. Important to its realization, he demonstrated that his double-gate structure could be fabricated using a conventional self-aligned silicon process. Today’s FinFET advanced logic technologies exhibit most of the principal operating concepts introduced by Hisamoto’s thin-body vertical-channel FET work.
An IEEE Fellow, Hisamoto is senior chief researcher, Hitachi, Ltd., Tokyo, Japan.
Gurtej Singh Sandhu’s pioneering achievements concerning patterning and materials integration have enabled the continuation of Moore’s Law for aggressive scaling of memory chips integral to consumer electronics products such as cell phones, digital cameras and solid-state drives for personal and cloud server computers. Sandhu initiated the development of atomic layer deposition high-k films for DRAM devices and helped drive cost-effective implementation starting with 90-nm node DRAM. Extreme device scaling was also made possible through his pitch-doubling process, which led to the first 3X-nm NAND flash memory. Sandhu’s method for constructing large-area straight-wall capacitors enabled the formation of double-sided capacitors that extended the scaling of important one-transistor, one-capacitor (1T1C) device technologies. His process for CVD Ti/TiN is still in use for making DRAM and NAND chips.
An IEEE Fellow, Sandhu is a Senior Fellow and Vice President of Micron Technology, Inc., Boise, ID, USA.
A visionary device physics researcher, Sorin Cristoloveanu saw the potential that silicon-on-insulator (SOI) technology held for the semiconductor industry in producing competitive microelectronics components with improved performance when others considered it a niche field. As early as 1976, he discovered key mechanisms of thin-body devices that have led to the development of transistors from the simplest (zero gate) to the most complicated (four gates). Among several concepts unveiled by his group, the demonstration during the 1980s that volume inversion occurs in all nano-body devices was revolutionary at the time and helped drive research that led to double-gate transistors and today’s tri-gate FinFET devices. His Pseudo-MOSFET method developed in 1992 has become an industry standard for wafer monitoring without having to actually fabricate devices. More recently, Cristoloveanu’s SOI expertise has led to innovative devices for low-power memory and sharp-switching circuits.
An IEEE Fellow, Cristoloveanu is the director of research at CNRS at IMEP-LAHC, Grenoble, France.
The innovations in logic transistor technology developed by Carlos H. Díaz have revolutionized the foundry industry and provided semiconductor companies the ability to bring devices to market more quickly and cost effectively. Díaz has successfully developed multiple generations of foundry technology from 0.18µm forward. He has demonstrated that it is possible to provide a flexible high-density transistor technology platform that supports multiple device segments with minimal burden on manufacturing. Of note is his work on the 28-nm generation, which meets the needs of both high-performance and low-power applications. The 28-nm high-K/metal-gate transistor technology has set the foundry industry standard in performance-power space coverage on a wide range of devices such as cellular/mobile computing, graphics processors, field-programmable-arrays, and central processing units.
An IEEE Fellow, Díaz is the director of Logic Technology Advanced Development Division with Taiwan Semiconductor Manufacturing Co., Hsinchu, Taiwan.
A pioneer of micro-electro-mechanical systems (MEMS) technology, Masayoshi Esashi developed ion sensitive FET (ISFET), which was commercialized as pH and CO2 catheters in 1980 and provided an early example of lab-on-a-chip technology. He developed and commercialized many MEMS innovations. His integrated capacitive pressure sensor and MEMS switch for LSI testers are based on wafer level packaging. Dr. Esashi’s resonating gyro was extended to yaw rate and acceleration sensors for vehicle stability control (VSC), and his electrostatically levitated rotational gyro, used for vibration measurement in railway cars, enables a more comfortable ride. Dr. Esashi’s MEMS-based optical scanner for platform door operation has also improved passenger safety.
An IEEE member, Dr. Esashi is a professor with the World Premier International Research Center/Advanced Institute for Materials Research (WPI-AIMR), Tohoku University, Sendai, Miyagi, Japan.
Sanjay Kumar Banerjee’s innovative contributions to metal-oxide field-effect transistors (MOSFETs) have driven advances in static random access memory (SRAM), dynamic random access memory (DRAM), and flash memory prevalent in today’s computers and mobile devices. Dr. Banerjee’s work has been integral to the continued scaling of MOSFETs and enabling low-power electronics. Dr. Banerjee was a leader in the development of the vertical trench transistor/capacitor used by Texas Instruments in the world’s first 4-Mb DRAM. His patented work on polysilicon-on-insulator MOSFETs advanced SRAM technology. He also demonstrated the first three-terminal MOS tunnel FET as well as the first high-k dielectric/silicon-germanium quantum dot gates for flash memories.
An IEEE Fellow, Dr. Banerjee is the Cockrell Regents Chair Professor of Electrical and Computer Engineering and director of the Microelectronics Center at the University of Texas, Austin, TX, USA.
Shinichi Takagi has driven performance improvements in metal oxide semiconductor field-effect transistor (MOSFET) technology with his insight on behavior of carriers in semiconductor devices. Dr. Takagi’s “universal mobility model” has been a key enabler of the continued scaling of electronic components. First presented in 1988, his model has provided a common framework for understating the transport mobility of carriers in the MOSFET inversion layer. The model has become a world standard highly cited in research and an important component of device simulators. His work on subband engineering of inversion layers focusing on strained silicon MOSFETs has important implications for sub-100-nanometer technology nodes. Dr. Takagi is also among the pioneers investigating higher-mobility materials such as germanium that will help the continued scaling of MOSFET devices when silicon technologies reach their scaling limits.
An IEEE member, Dr. Takagi is a professor with the Department of Electrical Engineering and Information Systems in the School of Engineering at the University of Tokyo, Japan.
Seeing the importance of silicon-on-insulator (SOI) technology early on when others did not, Jean-Pierre Colinge has been one of SOI’s strongest advocates with innovative contributions that have resulted in its widespread use. Dr. Colinge developed thin-film fully depleted SOI devices during the 1980s. He also invented the gate all-around device in 1990, which has become the ultimate silicon transistor. Also during the 1990s, Dr. Colinge fabricated the first nanowire transistors and explained their quantum effects. His pioneering work on advanced nanowire semiconductor devices has led to multiple-gate field-effect transistors. Today, Dr. Colinge continues to investigate multigate SOI technology for scaling to extremely small dimensions. His invention of a junctionless nanowire transistor in 2010 shows the potential for fabricating SOI devices with dimensions down to 5 nanometers. Dr. Colinge has educated countless engineers with "Silicon on Insulator Technology: From Materials to VLSI" (Kluwer Academic, 1991), which still serves as the standard introduction to SOI.
An IEEE Fellow, Dr. Colinge is currently with the Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan.
The groundbreaking work of Judy L. Hoyt and Eugene A. Fitzgerald involving strained silicon semiconductor materials has enabled the continued shrinking of integrated circuits, providing faster chips and devices. Based on Dr. Fitzgerald’s breakthrough of successfully fabricating strained (Si) on relaxed silicon germanium (SiGe) (stretching the Si crystal when applied to another material) in 1990, Dr. Hoyt and colleagues at Stanford pioneered the application of strained silicon to increase carrier transport properties in Si metal-oxide field-effect transistors (MOSFETs). In 1992, Dr. Hoyt used thin strained layers of Si on top of a relaxed SiGe artificial substrate to demonstrate the first fully functioning strained-channel MOSFETs. She later showed potential for the strain-engineered high-performance MOSFETs; results that inspired industry to harness strain in modern Si integrated circuits. Dr. Fitzgerald’s development of high mobility strained silicon on a low-defect relaxed SiGe spurred Dr. Hoyt’s work. He was able to solve defect formation problems to allow the joining of Si and Ge. He also demonstrated that highly strained materials could be deposited in small areas or, alternatively, strain-free SiGe could be deposited over large areas with a very low defect density. The ability to engineer highly relaxed and highly strained levels on Si led to Dr. Fitzgerald creating the first high-quality, high-mobility strained Si material.
An IEEE Fellow, Dr. Hoyt is a professor of electrical engineering and computer science at the Massachusetts Institute of Technology (MIT), Cambridge, and associate director of MIT’s Microsystems Technologies Laboratories.
An IEEE Member, Dr. Fitzgerald is the Merton C. Flemings-Singapore MIT Alliance Professor of Materials Engineering with the Massachusetts Institute of Technology, Cambridge.
Bijan Davari’s pioneering work in miniaturization of semiconductor devices changed the world of computing. Dr. Davari’s efforts during the mid 1980s led to the first generation of high-performance, low-voltage deep-submicron complementary metal-oxide semiconductor (CMOS) technology that enabled higher-speed computers and the portable computers and battery-powered handheld electronics we know today. His accomplishments displaced bipolar technology in IBM mainframes and enabled new high-speed UNIX servers, setting the standard for performance-optimized, low-power CMOS. Dr. Divari also led the development of innovations such as low-voltage switches, copper interconnect, silicon-on-insulator technology and high-performance logic-based embedded memory, making possible the computers that serve as the backbone of Internet data centers.
An IEEE Fellow and IBM Fellow, Dr. Davari is currently vice president of Next Generation Computing Systems/Technology at the IBM T.J. Watson Research Center, Yorktown Heights, N.Y.
Eric R. Fossum’s development of the active pixel image sensor based on CMOS technology has had a profound effect on digital photography, enabling and improving applications such as Web cams, cell phone cameras, high-end digital cameras, high-speed machine/medical vision systems, and automotive cameras. As an alternative to the charge-coupled device (CCD) sensor, Dr. Fossum’s CMOS active-pixel sensor took advantage of shrinking design rules and adapted successful CCD signal processing techniques to put an amplifier on each pixel of the image sensor to yield a high-quality image. Other advantages include better speed, reduced size, and less power consumption, which made it favorable for consumer devices. He co-founded Photobit Corporation in 1995 to accelerate the technology’s commercial use, and in 2001 the company was acquired by Micron Technology, one of the world’s largest suppliers of image sensors for mobile applications.
An IEEE Fellow, Fossum holds 119 U.S. patents and is currently a consultant for the Samsung Electronics Semiconductor Research and Development Center, where he leads a team of researchers in advanced imaging sensors.
Stefan K Lai?s contributions to the development and advancement of flash memory technology has spurred the success and popularity of several consumer electronics devices. Flash memory became a popular embedded storage solution for cellular phones in the 1990s, and has since contributed to the growth of several significant consumer electronics including digital cameras and digital media players. Dr. Lai?s work also stimulated the development of the USB flash drive, which has largely displaced floppy and other removable storage technologies, with capacities reaching several gigabytes. An IEEE Fellow, Dr. Lai holds seven patents and has published 34 papers. Dr. Lai is currently vice president, business Development of Ovonyx, Inc., Calif., and has also held various executive positions within Intel?s flash memory business unit and was a member of the technical staff at the IBM TJ Watson Research Center.
For over 30 years, James Plummer has made significant contributions in three main areas of electronic devices, namely, computer-aided design of silicon devices and fabrication processes, high-voltage power devices, and circuits, and novel devices for memory and logic applications. His early work focused on high-voltage integrated circuits (IC) and high-voltage device structures, including seminal contributions to the insulated gate bipolar transistor (IGBT), a device that has become a key component of the multi-billion-dollar high-power electronics industry. Dr. Plummer’s work on silicon process modeling led to the development of several generations of the process modeling program SUPREM, which today is the standard process-modeling tool used worldwide. Most recently, Dr. Plummer has worked on nanoscale silicon devices for logic and memory applications.
An IEEE Fellow, he has received numerous recognitions for his work, including IEEE awards, Semiconductor Research Corporation Awards, “best paper” awards, the Electrochemical Society’s 1991 Solid State Science and Technology Award, and election to the National Academy of Engineering.
As president and chief executive officer of the Semiconductor Business of Samsung Electronics Co., Ltd., Dr. Chang-Gyu Hwang has been the driving force in establishing Samsung as a leading global developer and supplier of random access memory, including dynamic (DRAM), and nonvolatile memories, NAND flash memory choices. Dr. Hwang’s leadership was critical to Samsung’s creation of the first 256M, 1G, and 4G DRAMs. He had a key role in developing NAND flash memory chips now commonly used in memory cards, USB flash drives, MP3 players, digital cameras, and mobile telephones. In 2002, he predicted that memory consumption and high-density memory use in mobile handsets and other consumer applications would grow faster with the advent of nanotechnology based on keen insight on the vast potential of NAND flash memory.
Dr. Hwang has co-authored more than 50 technical papers for journals and conferences and speaks frequently on industry trends before many academic and industry groups.
T.P. Ma's pioneering work in gate dielectrics increased integrated circuit operating speed and reliability, lowered cost per function, and raised density by a significant factor. Gate dielectrics are a critical element in metal oxide semiconductor (MOS) devices, the building blocks of today's silicon chips. Dr. Ma, the Raymond John Wean Professor of Electrical Engineering and chair of the Electrical Engineering Department at Yale University in New Haven, Connecticut, recognized early the importance of gate tunneling current in MOS behavior. The semiconductor industry now recognizes this as a major issue in scaling future MOS technology. He is co-author with Paul V. Dressendorfer of "Ionizing Radiation Effects in MOS Devices and Circuits." This has been hailed widely by colleagues as the most authoritative and comprehensive work on the subject.
A Fellow of the IEEE, Dr. Ma is a member of the U.S. National Academy of Engineering and has received the IEEE Electron Devices Society's Paul Rappaport Award.
Demonstrating visionary leadership for more than 30 years, Krishna Saraswat’s influence extends from fundamental research of silicon oxidation to system-level studies of wiring delays and chip performance. Consistently ahead of his time, Dr. Saraswat's has made fundamental contributions on device structures, new materials, and process technology of silicon devices and integrated circuits. These contributions have helped in continued scaling of device dimensions and improvement in the performance of integrated circuits. A Professor of Electrical Engineering and the Rickey/Nielsen Professor of Engineering at Stanford University in Stanford, California, Dr. Saraswat also serves as the Associate Director of the National Science Foundation / Semiconductor Research Corporation – Engineering Research Center for Environmentally Benign Semiconductor Manufacturing. Dr. Saraswat’s pioneering discoveries have repeatedly resulted in seminal advances for industry. One important example is his early 1980s work in WSi2 polycide gate MOS technology, in which he broke with prevailing trends to successfully focus on chemical vapor deposition (CVD) technology. He later developed an Al/Ti metallization process, which quickly became an industry standard. Dr. Saraswat has provided invaluable leadership on interconnect scaling and modeling/simulation, notably through his farsighted delineation of the RC delay in an article two decades ago. In the late 1980s, he focused on single wafer manufacturing, developing equipment and simulators for rapid thermal processing, deposition, and etching. Since the mid-1990s, Dr. Saraswat has been working on scaling MOS technology to nm range and on new concepts of 3-D integrated circuits with multiple layers of heterogeneous devices. He also is currently researching environmentally benign semiconductor manufacturing. Born on 3 July 1947 in Pilani, India, Krishna Saraswat earned a bachelor of engineering degree in electronics from the Birla Institute of Technology and Science in Pilani, India, and a master of science degree in electrical engineering from Stanford University. After two years with Texas Instruments in Dallas, Texas, he returned to Stanford for his doctorate, completed in 1974, and to work as a research associate and subsequently as a professor in electrical engineering.
An IEEE Fellow and member of the Electrochemical and the Materials Research Societies, Dr. Saraswat has received the Electrochemical Society’s Thomas D. Callinan Award and two gold medals for undergraduate excellence while attending the Birla Institute of Technology and Science. He is the author or co-author of more than 400 technical papers and is the recipient of several Best Paper Awards, including from the IEEE Electron Devices Meeting, the Annual Device Research Conference and from the Journal of the Electrochemical Society. Dr. Saraswat resides in Saratoga, California, with his wife, Sonia and their two sons, Prashant and Vivek. His outside interests include traveling, hiking, photography, music, and tennis.
Close to a billion microprocessors have been manufactured employing Mark T. Bohr’s work. As an architect and innovator for Intel’s CMOS technology, Mr. Bohr’s leadership has been a vital element of virtually every CMOS or BiCMOS technology at Intel since the 1980s. Since joining Intel's Portland Technology Development group in 1978, Mr. Bohr has led the development of simple yet elegant processes that facilitate large volume production of top microprocessors. His work helped to usher in the CMOS DRAM era, and his work on BiCMOS logic technology paved the way for Intel’s successful Pentium microprocessors. He has helped develop many groundbreaking technologies including: modern CMOS technology in 1981, CMOS DRAM technology in 1983, BiCMOS logic technology in 1992, logic technologies ranging from 0.8mm to 0.13mm and beyond, and the recent 90-nm process technology employed by microprocessor and communication products. The features and techniques defined by Mr. Bohr have helped give Intel industry-leading process and product capabilities. Mark T. Bohr was born in Westchester, lll., on 31 October 1953. He received a bachelor’s degree in industrial engineering in 1976 and a master’s degree in electrical engineering in 1978, both from the University of Illinois, Champaign-Urbana. Currently, he directs process architecture and integration with a special focus on development activities for Intel's 65 nm process technology. Mr. Bohr has always been generous in sharing his expertise with the technology community. He has taught courses inside Intel and at conferences, given presentations and published work that has provided the benchmarks against which high performance CMOS technologies are measured.
A Senior Member of the IEEE, Mr. Bohr has served on paper selection committees for the IEEE International Electron Devices Meeting and the Symposium on VLSI Technology. He holds 19 patents for his work on integrated circuit processing, and has been awarded Intel’s highest technical honor—designation as an Intel Fellow. In 1998, he received the Distinguished Alumnus Award from the University of Illinois Department of Electrical and Computer Engineering.
Known for his intuitive approach to complex technologies, Dr. Dimitri A. Antoniadis has had a tremendous effect on several areas of microelectronics technology, especially in field-effect controlled quantum-effect devices and silicon process modeling. At Stanford in the mid-1970s, Dr. Antoniadis played a key role in developing the SUPREM I and II, which became the first widely used process simulation tools in industry and the basis of programs in use today. After joining the faculty of the Massachusetts Institute of Technology (MIT) in 1978, Dr. Antoniadis led a program that proved and quantified the dual vacancy-interstitialcy diffusion mechanism of substitutional dopant atoms in Si. This dual diffusion model remains at the core of all modern process simulators. In the 1980s, Dr. Antoniadis, with his colleagues at MIT, established a bold research program into field-effect devices that took advantage of cutting-edge extreme submicron lithography techniques. The program produced many groundbreaking demonstrations, including those of lateral-surface superlattice and quasi-one-dimensional channels in silicon and GaAs, and the first silicon single-electron transistor. Working with his students, Dr. Antoniadis has made many pioneering contributions to Bulk-Silicon and Silicon-on-Insulator MOSFET research that had major impact on key aspects of device design for today’s high-perfomance silicon MOSFETs. His current research focuses on the physics and technology of extreme-submicron Si, SOI, and Si/SiGe MOSFETS. He is author and co-author of more than 200 technical articles. Dimitri A. Antoniadis was born on 1 January 1947, in Athens, Greece. He received his B.S. in Physics from the National University of Athens in 1970, and his Ph.D. in Electrical Engineering from Stanford University in 1976. In 1978, Dr. Antoniadis joined the faculty at MIT where co-founded and was the first Director of the MIT Microsystems Technology Laboratories. He later directed the SRC MIT Center of Excellence for Microsystems Technology. Currently, he holds the Ray and Maria Stata Chair in Electrical Engineering and directs the Multi-University Focus Research Center for Materials Structures and Devices.
Dr. Antoniadis is a Fellow of the IEEE. His awards include the IEEE Paul Rappaport Award and the Solid State Science and Technology Young Author Award of the Electrochemical Society. At the IEEE, he has served as Editor of the IEEE Transactions on Electron Devices, and on various technical committees.