Standards Education tutorials are designed to be completed in under one hour. Each section contains a short mastery quiz exercise at the end.
The material in the tutorials is based upon work supported by the National Science Foundation under Grant No. 0442313. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF).
This tutorial addresses the subject of technical standards, ranging from architecture and operations to physical, environmental, and electrical aspects of a product or service.
This is the "core" tutorial created by the Standards in Education Project and covers all of the basics of standards and standards development across disciplines.
This tutorial addresses the role standards played in the development and delivery of cellular telephony. It provides background on the factors and forces that have shaped air interface standards and discusses the struggle to reach the goal of one internal air interface standard.
Considerable attention is paid to the objectives of competing interests that cooperate in the development of standards and attempt to influence the process according to their business goals.
This tutorial addresses the role standards play in the development of electrical power systems.
Standards for electrical power systems design, installation, and operation are developed by many organizations for different purposes. Some standards cover design features and details, some determine interoperability, some establish means by which to achieve consistency and reliability of equipment, and others ensure installations are made safe and equipment and circuits are operated and maintained safely.
SystemVerilog is a Hardware Description and Verification Language used by chip designers (Hardware Design and Verification Engineers) for describing the structure and behavior of electronic circuits. It is an IEEE standard known officially as IEEE 1800TM-2005.
This tutorial provides an introduction to the SystemVerilog Standard, explores the benefits of SystemVerilog over other languages (VHDL, Verilog HDL, VERA, SystemC), and provides an overview of its design, testbench, and assertion constructs.