EDS

Technical Briefs

2024 IEEE International Electron Devices Meeting Spotlights Advances in Critical Semiconductor Technologies with the Theme “Shaping Tomorrow’s Semiconductor Technology” (part 2)

by Kang-ill Seo, IEDM 2024 Publicity Chair and Gaudenzio Meneghesso, IEDM 2024 Publicity Co-Chair

The 2024 IEEE International Electron Devices Meeting (IEDM) was held on 7-11 December in San Francisco, with online access to recorded content available afterward. The EDS Newsletter issue of January 2025 presented a general overview of the conference. This Technical Brief presents greater details of selected papers reflecting the conference theme: “Shaping Tomorrow’s Semiconductor Technology.” The noteworthy papers were only listed in the previous issue. They can be grouped into six thematic areas.

In the paper #2.1, “2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications,” the TSMC team unveiled the world’s most advanced logic technology. It is the company’s forthcoming 2nm CMOS (i.e., N2) platform designed for energy-efficient computing in AI, mobile, and HPC applications. It offers a 15% speed gain (or 30% power reduction) at >1.15x chip density versus the most advanced logic technology currently in production, TSMC’s own 3nm CMOS (N3) platform, introduced in late 2022. The new N2 platform features GAA nanosheet transistors; middle-/back-end-of-line interconnects with the densest SRAM macro ever reported (~38Mb/mm²); and a holistic, system-technology co-optimized (STCO) architecture offering great design flexibility. That architecture includes a scalable copper-based redistribution layer and a flat passivation layer for better performance, robust CPI, seamless 3D integration, and through-silicon vias (TSVs) for power/signal with F2F/F2B stacking. The authors said the N2 platform was in risk production and is scheduled for mass production in the second half of 2025. The N2P (5% speed-enhanced version of N2) targets to complete qualification in 2025 and mass production in 2026.

The cross-sectional image shows that the N2 platform’s Cu redistribution layer (RDL) and passivation seamlessly integrate 3D technologies (Paper #2.1, “2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications,” G. Yeap et al, TSMC).

In the paper #2.2, “Silicon RibbonFET CMOS at 6nm Gate Length,” Intel researchers showed that silicon can continue to support the extreme gate length scaling that future technology nodes require. They described how they built RibbonFET CMOS transistors (Intel’s version of nanosheets) with 6nm gate lengths at 45nm contacted poly pitch (CPP, the spacing between adjacent transistor gates), with no electron mobility degradation. The researchers showed that electron mobility doesn’t degrade until 3nm silicon thickness (T_Si), below which electron scattering due to surface roughness becomes an issue. They described how they achieved good short channel control (DIBL≤100mV/V at T_Si<4nm), with extremely low threshold voltage at these gate lengths through workfunction engineering. The work showed that 3nm is a practical limit of T_Si scaling for RibbonFETs.

Drain-induced barrier lowering (DIBL) vs. silicon thickness (T_Si) at L_G = 18nm shows a reduction as T_Si is scaled from 10nm to 1.5nm. DIBL reduction saturates at T_Si < 4nm, below which very low gain is obtained. PMOS DIBL is higher than NMOS DIBL at the same T_Si. Also shown are TEM micrographs of a single ribbon (1NR) transistor with various T_Si down to 1.5nm (Paper #2.2, “Silicon RibbonFET CMOS at 6nm Gate Length,” A. Agrawal et al, Intel).

The paper #2.5, “First Demonstration of Monolithic CFET Inverter at 48nm Gate Pitch Toward Future Logic Technology Scaling,” from TSMC, unveiled a practical, monolithic CFET architectural approach for logic technology scaling. They described how they built the first fully functional advanced CFET inverter at an industry-leading 48nm gate pitch. The inverter (a building block for logic circuits) was made from stacked n-FET-on-p-FET nanosheet transistors, now with backside contacts and interconnect for improved performance and increased design flexibility. The devices they built exhibited well-balanced voltage transfer characteristics up to 1.2V, and a good subthreshold slope of 74-76mV/V for both n and p devices. The researchers said that this successful demonstration of fully operational CFET inverters marks an important milestone in the progress of CFET technology, paving the way for future logic technology scaling and the advancement of power, performance, area, and cost (PPAC) attributes.

A TEM cross-section of the monolithic CFET interconnect architecture. The top image details the monolithic CFET contacts and local interconnects, showing a vertical metalized drain local interconnect (vMDLI); metalized drain (MD), and via (VD) from the frontside process, and backside metalized drain (BMD) and backside via (BVD) from the backside process. The bottom image focuses on the backside gate via (BVG) implementation (Paper #2.5, “First Demonstration of Monolithic CFET Inverter at 48nm Gate Pitch Toward Future Logic Technology Scaling,” S. Liao et al, TSMC).

The paper #6.1, “Oxide-Semiconductor Channel Transistor DRAM (OCTRAM) with 4F² Architecture,” reported a joint work of Kioxia and Nanya Technology teams aimed, following industry efforts, at developing denser 4F² DRAM made with different materials to overcome conventional silicon 6F² DRAM major challenges: patterning the extremely small features of DRAM memory cells and suppressing “row hammer” electrical interference from nearby cells. The authors presented a new type of 4F² DRAM, comprising GAA IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) and a new integration scheme, where the heat-sensitive transistors are placed on the top of high aspect-ratio capacitors instead of on the bottom, to reduce the thermal impact from BEOL processing below. The vertical architecture also fully suppresses the “row hammer” interference, because the active region isn’t shared with adjacent cells. The InGaZnO VCT achieved more than 15µA/cell ON current and 1aA/cell OFF current. The researchers demonstrated the technology by successfully building a 275Mbit array, demonstrating its potential for future high-density, low-power DRAM technologies.

(a) Panoramic view of the OCTRAM, 4F2 DRAM with InGaZnO VCT; (b) Cross-sectional TEM for the InGaZnO VCT on high aspect ratio capacitor; (c) Top view of the capacitor array (Paper #6.1, “Oxide-Semiconductor Channel Transistor DRAM (OCTRAM) with 4F² Architecture,” S. Fujii et al, Kioxia Corp./Nanya Technology Corp.).

In the paper #34.2, “Unraveling BTI in IGZO Devices: Impact of Device Architecture, Channel Film Deposition Method and Stoichiometry/Phase, and Device Operating Conditions,” imec researchers reported their extensive studies on threshold voltage instabilities in IGZO TFTs that have gained increasing interest for DRAM devices and for non-volatile DRAM replacements, due to their low leakage current. The reported studies revealed that the threshold voltage instabilities strongly depend on factors like device architecture, channel deposition, IGZO stoichiometry and phase, and the waveform used during device operation. The researchers identified two potential solutions to mitigate threshold voltage changes: using indium-poor films (In~5%) and restricting the duty cycle of the operating waveform to below 25%. They said these approaches are key enablers for the development of future DRAM technology.

Architectures of the (a) bottom-gated and (b) top-gated devices studied (Paper #34.2, “Unraveling BTI in IGZO Devices: Impact of Device Architecture, Channel Film Deposition Method and Stoichiometry/Phase, and Device Operating Conditions,” A. Chasin et al, imec).

The National Taiwan University team described in the paper #4.2, “Uniform and Fatigue-Free Ferroelectric HZO with Record E_BD of 6.3MV/cm and Record Final 2P_r of 64μC/cm² at Record 5E12 Endurance Using Low Lattice Misfit (2.9%) β-W,” a step forward in addressing uniformity and reliability issues in hafnium zirconate (HZO) gate stacks. Such structures are considered for use in non-volatile memories due to the HZO ferroelectric characteristics, compatibility with CMOS processing, and suitability for scaling. The researchers built metal-ferroelectric-metal (MFM) capacitors with β-W electrodes that exhibited a low lattice mismatch (2.9%) with HZO and demonstrated fatigue-free endurance with record high breakdown electric field. Their work opens a path toward better-performing HZO-based devices.

The bottom β-W/HZO/top β-W MFM capacitor. The TEM image (left) shows the metal-ferroelectric-metal structure. The high-angle annular dark-field (HAADF) image (right) shows the superlattice structure in the ferroelectric HZO layer (Paper #4.2, “Uniform and Fatigue-Free Ferroelectric HZO with Record E_BD of 6.3MV/cm and Record Final 2P_r of 64 μC/cm² at Record 5E12 Endurance Using Low Lattice Misfit (2.9%) β-W,” G.-H. Chen et al, National Taiwan University).

Tsinghua University researchers described in the paper #5.3, “IGZO/TeO_x Complementary Oxide Semiconductor-based CFET for BEOL-Compatible Memory-Immersed Logic,” their work to build the first 3D-integrated chip with metal-oxide-based CFETs for memory-immersed logic applications. The 3D monolithically integrated chip comprises: 1) a layer of front-end Si-CMOS logic, 2) a layer of resistive random access memory (RRAM), and 3) an oxide-semiconductor-based CFET layer, featuring an IGZO n-MOS transistor and a TeO_x p-MOS transistor. The three layers are tightly optimized for matrix-vector multiplication in memory, and for data movement by memory-immersed logic, thus significantly reducing area, delay, and energy consumption by 55.1%, 24.8%, and 44.9%, respectively, compared to 2D CIM circuits.

In the paper #38.1, “Analog Computation in Ultra-High Density 3D FeNAND for TB-Level Hyperscale AI Models,” SK hynix researchers reported on how they achieved for the first time analog computation in ultra-high-density 3D vertical ferroelectric NAND (FeNAND) devices. They used gate stack engineering techniques to improve the analog switching properties of 3D FeNAND cells and achieved an unprecedented ≥256-conductance-weight levels/cell. The 3D FeNAND arrays improved analog computing-in-memory (CIM) density by 4000× versus 2D arrays and demonstrated stable multiply-accumulate (MAC) operations with high accuracy (87.8%) and 1000× higher computing efficiency (TOPS/mm²) versus 2D arrays. This work provides an efficient method to implement the processing of hyperscale AI models in analog CIM chips for edge computing applications, where speed and low power operation are the critical requirements, not extreme accuracy.

The chip architecture, consisting of three functional layers: Si CMOS logic, analog RRAM-based CIM, and OS-CFET-based memory immersed logic (CMIL) that integrates an ultralow-leakage IGZO-NFET with a CFET-based inverter and logic gates (Paper #5.3, “IGZO/TeO_x Complementary Oxide Semiconductor-based CFET for BEOL-Compatible Memory-Immersed Logic,” T. Liu et al, Tsinghua University).

A TEM picture of the 3D FeNAND: (left) a top-down view, (right) a cross-sectional view at low magnification (Paper #38.1, “Analog Computation in Ultra-High Density 3D FeNAND for TB-Level Hyperscale AI Models,” J.-G. Lee and W.-T. Koo et al, SK hynix).

Intel researchers reported in the paper #9.3 “30nm Channel-Length Enhancement-Mode GaN MOSHEMT Transistors on a 300mm GaN-on-TRSOI Engineered Substrate,” on the industry’s first high-performance scaled E-mode GaN MOSHEMT transistors, fabricated on a 300mm GaN-on-TRSOI (“trap-rich” SOI) substrate. MOSHEMTs combine the benefits of silicon MOSFETs and III-V semiconductors. To demonstrate the technology’s versatility, they built various GaN MOSHEMTs with and without gate/source-field plates and multiple stacked gates integrated on the 300mm GaN-on-TRSOI wafer. A 30nm-gate source-field plated GaN MOSHEMT RF transistor with a gate-to-drain separation of 400nm and a source-field plate (length = 100nm) drove high currents exceeding 1mA/µm, and handled drain voltage swings as high as 12V. The RF small-signal performance of the GaN MOSHEMT technology was exceptional, demonstrating high cut-off frequencies (f_T = 190GHz and f_MAX = 532GHz), bringing 6G wireless communications closer to reality. The results showed that substrate engineering is crucial for the improvement of RF and power performance.

A schematic of the source-field plated enhancement-mode high-k gate dielectric GaN MOSHEMT transistor architecture, fabricated on the 300mm GaN-on-TRSOI wafer. The submicron (LSFP=100nm) feature size for the field-plate adds negligible parasitic capacitance. Its close proximity (~50nm) and placement near the two-dimensional electron gas (2DEG, marked with a dashed line) enables effective drain field control (Paper #9.3, “30nm Channel-Length Enhancement-Mode GaN MOSHEMT Transistors on a 300mm GaN-on-TRSOI Engineered Substrate,” H.W. Then et al, Intel).

In the paper #25.6, “10kV, 250°C Operational, Enhancement-Mode Ga₂O₃ JFET with Charge-Balance and Hybrid-Drain Designs,” a Virginia Tech-led team described how they built a lateral Ga₂O₃ junction-gate field-effect-transistor (JFET) employing high p-doped NiO for E-mode operation, and hybrid-drain structures for electric field management, featuring breakdown voltages (BVs) exceeding 10kV, and specific on-resistance values of 92 and 703mΩ·cm² for thick- and thin-channel designs, respectively. The devices demonstrated not only the best figures-of-merit (FOM) of all >3kV ultra-wide bandgap (UWBG) transistors but also the first 250°C operation and 3kV reliability data of all high-voltage transistors other than Si and SiC devices. The authors said that the results of the work, the unveiled physics, and trade-offs can guide the development of future devices for high-voltage, high-temperature applications.

Top: a 3D schematic of the Ga₂O₃ JFET. The SU-8 passivation layer is partially removed to show the internal structure. Bottom: a cross-sectional view illustrates the key geometric parameters and charge-balance (CB) condition. (Paper #25.6, “10kV, 250˚C Operational, Enhancement-Mode Ga₂O₃ JFET with Charge–Balance and Hybrid–Drain Designs,” Y. Qin et al, Virginia Tech/U.S. Naval Research Laboratory/Novel Crystal Technology, Inc.).

A team led by researchers from Seoul National University presented in the paper #18.7, “Intelligent Multimodal Sensors Integrating Gas, Barometric Pressure, and Temperature Sensing,” a smart multimodal device with energy-efficient in-memory computing-based processing on a single, compact substrate. By utilizing an in-memory computed capacitive binarized neural network, the sensor consistently delivers high-precision gas detection with 97.8% accuracy, even under varying conditions. It also offers highly linear and sensitive barometric pressure readings and robust gas identification capabilities in real-world environments, with great potential for precise environmental monitoring and safety applications.

(a) A schematic diagram of the integrated barometric pressure sensor array and AND-type NVM array, (b) SEM image of the barometric pressure sensing system (Paper #18.7, “Intelligent Multimodal Sensors Integrating Gas, Barometric Pressure, and Temperature Sensing,” G. Jung et al, Seoul National University/Ministry of Science and ICT).

In the paper #41.6, “A Color Image Sensor Using 1.0μm Organic Photoconductive Film Pixels Stacked on 4.0μm Si Pixels for Near-Infrared Time-of-Flight Depth Sensing,” Sony researchers described a way to acquire both RGB images and ranging information on a single chip, without interference between the two. They stacked RGB pixels (made of panchromatic organic photoconductive film, which absorbs visible light) onto near-infrared (NIR) indirect-time-of-flight (iToF) Si pixels. The RGB pixels are 1.0μm Bayer pixels (color filters), and the ranging pixels are 4.0μm iToF pixels. The organic photoconductive film was designed to suppress NIR wavelength mixing with RGB pixels, while the transparent wires and RGB filter suppress color mixing with the iToF pixels, ensuring high quantum efficiency. The sensor demonstrated simultaneous, parallax-free acquisition of high-resolution RGB and ranging information with good color reproduction under both visible and NIR light conditions.

Images captured by a color image sensor using RGB pixels stacked on iToF pixels: (a) an RGB image, (b) a depth image (Paper #41.6, “A Color Image Sensor Using 1.0μm Organic Photoconductive Film Pixels Stacked on 4.0μm Si Pixels for Near-Infrared Time-of-Flight Depth Sensing,” T. Ohkubo et al, Sony).

The National Tsing Hua University-led team described in the paper #18.2, “Design and Implementation of a Novel Dual-Gap CMOS-MEMS CMUT Array,” an innovative CMOS-MEMS capacitive micromachined ultrasonic transducer (CMUT) array. It provides a trade-off between the transmitter (TX), which requires a large transducer gap to improve transmitting efficiency, and the receiver (RX), which needs a small gap to enhance the receiving sensitivity. For that, it features dual transduction gaps (180nm and 400nm) on a standard CMOS platform. The design prioritizes excellent transceiving efficiency at low DC bias voltages. Experimental results suggest a high electromechanical coupling strength and superior ultrasonic transmitting efficiency of 16.7kPa/V/mm², and a receiving sensitivity of 57mV/kPa, in underwater acoustic experiments. These and other findings collectively underscore the potential of dual-gap CMUT-on-CMOS technology for ultrasonic applications.

A cross-sectional schematic of the proposed CMUT chip and the list of the materials used to build the devices (Paper #18.2, “Design and Implementation of a Novel Dual-Gap CMOS-MEMS CMUT Array,” H.Y. Chen et al, National Tsing Hua University/UC-Berkeley).

Samsung researchers reported in the paper #17.1, “Ab-initio Screening of Amorphous Chalcogenides for Selector-Only Memory (SOM) through Electrical Properties and Device Reliability,” extensive ab initio computer modeling to understand the potential of various material combinations in ternary compounds A_xB_yX_100-x-y of amorphous chalcogenides for realization of SOMs combining DRAM-like read/write speeds with non-volatile operation. By investigating threshold voltage drift and the drift of the memory window (the voltage difference between a device’s “on” and “off” states) as they simultaneously optimized selector and memory characteristics, they established key screening parameters. Their modeling took into account bonding characteristics, thermal stability, electrical properties, and device reliability. This systematic approach enabled them to identify 18 promising material candidates to use in physical experiments, out of 3,888 possibilities studied. This methodology is expected to be used to find candidate materials for other device applications, thus accelerating semiconductor R&D productivity.

A steady-state temperature simulation of an active RISC-V core on a chip using DeepSim’s Mariana solver (Paper #26.4, “AI-Accelerated Atoms-to-Circuits Thermal Simulation Pipeline for Integrated Circuit Design,” A. Gabourie et al, DeepSim/UC-Davis/Stanford Univ.).

The four-stage screening process for identifying suitable amorphous chalcogenide materials for SOM applications. Bonding characteristics, thermal stability, electrical properties, and device reliability were studied. Numbers on the left side denote populations of the material combinations screened out after subsequent qualification steps starting from the initial 3888 candidates (Paper #17.1, “Ab-initio Screening of Amorphous Chalcogenides for Selector-Only Memory (SOM) through Electrical Properties and Device Reliability,” H.-J. Sung et al, Samsung).

The DeepSim, Inc.-led team described in the paper #26.4, “AI-Accelerated Atoms-to-Circuits Thermal Simulation Pipeline for Integrated Circuit Design,” how they used AI modeling and GPU computing power to overcome the limitations of existing simulation methods to develop the first AI-accelerated, multiscale, atoms-to-circuits thermal simulation pipeline. They claimed it would enable IC designers to accurately model temperature in the designs and potentially overcome emerging thermal challenges in 2D/3D ICs. First, they described their atoms-to-transistors approach, based purely on ab initio atomistic modeling of materials, and how they used it to predict the temperature distribution of an Intel 16 FinFET. Then, they discussed a transistors-to-circuits approach, building from a FinFET thermal model a full-detail nanoscale-resolution temperature prediction of an active RISC-V core in <10 minutes. It was a result that existing non-AI-based tools can’t match. It showed using AI-driven simulations to understand heat transport, all the way from atoms to circuits.

We are aware that the reviews presented above are very brief and subjective. However, we hope that they will encourage you to seek information on topics of interest to you in the 2024 IEDM materials, which are available through IEEE Xplore. Of course, we are looking forward to meeting you at IEDM in 2025! For the IEDM registration and other information, visit www.ieee-iedm.org. Follow also IEDM via social media:

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The 7th IBM IEEE CAS/EDS AI Compute Symposium was held at the T. J. Watson Research Center on 19 November 2024, as a hybrid in-person and virtual event. The event was extremely successful and well attended by over 900 folks worldwide (in-person and virtual). The symposium featured 9 distinguished speakers (8 from industry and 1 from academia), 30 in-person student posters, best poster awards, and a panel discussion. The registration list comprised citizens of 69 countries. The theme of the symposium, “From Chiplets to Future AI Ecosystems” turned out to be an opportune and important topic for the direction of the semiconductor industry. The symposium served as an educational and brainstorming session for industry/academia/students across the world. The symposium covered a range of topics including AI algorithms; technology requirements, such as circuits, memory requirements, chip, and chiplet architecture; advanced packaging technologies; HBM; and emerging AI applications, e.g., augmented and virtual reality. Dr. Rajiv Joshi, IEEE Fellow, opened the symposium with welcoming remarks along with the goals and accomplishments of this symposium under the auspices of CAS, EDS, and IBM. He also highlighted the industry-CAS-EDS participation throughout the symposium history.

Dr. Sriram Raghavan, Vice President at IBM Research, opened the first keynote presentation titled “From Generative AI to Generative Computing.” The main idea was to highlight how Large Language Models (LLMs) impact AI’s future. He focused on key concepts such as the impact of model size, model customization, inference scaling, and generative computing. Recent improvements in the LLMs were described. While a brute force method to improve a model’s capability is to increase the model size, these larger models are often only superior for the near term. In short, newer customized Small Language Models (SLMs) can often outperform the previous generation LLMs. IBM’s LLM offering called Granite was compared with many LLMs on tasks spanning instruction following, reading comprehension, reasoning, code, math, multilingual tasks, and more. The Granite models showed significant improvements over many leading models. Dr. Raghavan then described model customization using techniques including taxonomy-based skill and knowledge representation, synthetic data generation with a teacher model, and artificial data validation using the critic model. Next, a promising technique for model performance improvement, referred to as Inference Scaling, was discussed. This approach in essence consists of multiple inferences that call for a single query to make the LLM “think more deeply.” Finally, the prospects of generative computing were discussed including the potential of interleaving conventional imperative computing and generative computing.

Dr. Jae-Yong Park, Vice President of Technology at Samsung, described “Transforming Semiconductor Manufacturing with AI: From Chiplets to Autonomous Fabs and Digital Twins.” He stressed that the semiconductor industry is transforming through artificial intelligence (AI) and machine learning (ML), particularly in memory and logic manufacturing. His talk explored the impact of generative AI, including multimodal foundation models and retrieval-augmented generation (RAG), on advanced process and equipment control in semiconductor manufacturing. Further, the talk described how these AI approaches enhanced yield, quality, and efficiency by enabling real-time optimization, predictive maintenance, and adaptive control strategies. The implementation of multimodal AI for integrating diverse data types in process control and defect detection, the use of RAG systems for context-aware decision-making, and the deployment of on-device AI for responsive equipment-level control were discussed. The vision of AI-driven autonomous fabs and digital twins was presented as the industry’s ultimate goal, accelerating next-generation chip development. This presentation offered crucial insights into the future of semiconductor manufacturing for industry professionals and researchers in this rapidly evolving field.

Dr. Lalitha Imaneni, Vice President of Semiconductor Research & Development at Intel, showed how “Chips to Chiplets: ‘Moore’ Value Beyond Transistor Scaling” would be possible. It is widely accepted that AI has exploded and is driving aggressive application growth in everything from consumer to high-end server markets. This is fueling hardware architecture to respond to an exponential demand for more computing resources with better access to more memory. As computing needs have skyrocketed, the semiconductor industry is looking for innovations to augment what can be achieved with Moore’s law to meet this exponential demand. This is driving innovation in architecture and technology, including packaging technology. Semiconductor yield and manufacturability at finer dimensions are leading designers to disaggregate monolithic die into smaller chiplets. This ‘chipletization’ and ‘re-aggregation’ with advanced packaging technologies requires a concerted industry-wide effort. Systems and standards that allow designers and product architects to mix and match chiplets and features seamlessly are critical. In addition, designers need to be able to make complex trade-offs in architecture, performance, cost, and manufacturability with packaging at the center of it all. Dr. Imaneni discussed how packaging addresses the need for more computing and memory with innovations while keeping the total cost of ownership concerns front and center of our solutions.

Dr. Unoh Kwon, Vice President and Head of HBM PI at SK hynix, presented work related to “High Bandwidth Memory (HBM) in the AI Era: Empowering Memory-Centric AI Innovation.” He described five steps to go from AI to Artificial Generative Intelligence (AGI). Step 1: Chatbot (current AI with conversational language); Step 2: Reasoner (AI having human-level problem solving); Step 3: Agent (AI systems that can take actions); Step 4: Innovator (AI that can help in innovation); and Step 5: Organizer (AI that can do work as an organizer). To reach these steps, the biggest challenges for artificial intelligence (AI) processors are performance, power, memory bandwidth, and cooling. In particular, power-efficient memories with high capacity and bandwidth are keys. He showed the impressive progress of SK hynix going from GDDR6 to HBM3E. The capacity, bandwidth, and power efficiency were increased by 6x, 18.3%, and 70% respectively. The further increase in memory demand will lead to HBM4 and beyond which will pose both implementation challenges and provide system opportunities. Overall, HBM-like solutions and advanced packaging technology are essential to meet AI processor demand.

Dr. Tom Gray, Senior Director of Circuit Research at NVIDIA, delivered a talk on “Circuit Research from Chips to Chiplets to Enable Next Generation AI Datacenters.” AI applications on GPU systems have exploded with an almost unlimited appetite for computing. Single-chip inference performance has increased 1000x over the last 10 years with improvements spanning architecture to circuits. Tens of thousands of datacenter-connected GPUs are needed for training and inference of state-of-the-art generative AI models. Bandwidth density requirements increase on the order of 2x in each generation and power delivery is strained at all levels, from on-die to datacenter. This creates a critical need for future research addressing scaling and power reduction in all areas including compute/memory, communication, power delivery, and heat removal. In this talk, Dr. Gray explored what is ultimately needed for the design and deployment of these systems at the circuit and hardware level including circuits for computing, electrical and photonic interconnects, memory system design and scaling, packaging and stacking, power delivery and conversion at the rack, board, and die level, and thermal design and limitations.

Dr. Ramesh Narayanaswamy, Senior Architect R&D at Synopsys, presented “Generative AI for Chip Design: Need, Opportunities, & Challenges.” He began by motivating the need for AI in chip design by mentioning that the decline in electrical engineering enrollment is expected to result in a 20-30% talent shortage by 2030. Meanwhile, the increasing compute requirements driven by Generative AI (GenAI) and HPC demand a 30-40% shorter design development schedule. GenAI provides an opportunity to automate and optimize many of the manual processes in the design cycle. Next, he described how GenAI agents and agentic tools can be combined to create a designer’s assistant for tasks like assertion creation and performance optimization. Dr. Narayanaswamy pointed out GenAI challenges, such as limited datasets and evaluation benchmarks in the public domain, and suggested that industry-academic collaboration on datasets and benchmarks will be needed. His talk concluded by pointing out several GenAI for chip design research topics.

Prof. Andreas G. Andreou, Professor of Electrical and Computer Engineering at Johns Hopkins University, spoke on “Neurochiplets and Silicon Brains in 3D CMOS.” The brain is undoubtedly the world’s most powerful computer for solving problems in machine perception (vision, speech, language) and machine learning. Over the last half-century computer scientists, architects, and engineers have envisioned building computers that match the parallel processing capabilities of biological brains for perception and cognitive computing. Three-dimensional integration through wafer stacking and 2.5D assembly is an alternative to technology scaling and monolithic integration that increases the number of transistors and short-range interconnect per unit area thus improving energy efficiency.

Prof. Andreou began the talk by describing the history of chiplets research. He then described innovative brain-inspired chip designs his group at Johns Hopkins developed spanning the early days of chiplet research to more recent chip tape-outs. Prof. Andreou described nano-Abacus, a chipset-based neuromorphic architecture for accelerating computing, hardware AI inference, and machine intelligence. SEE-THINK Chiplets were another family of designs discussed. Among other novel contributions, Prof. Andreou presented work on silicon tape-outs for spiking neural network applications based on Verilog generation using LLMs.

Dr. Tony Chan Carusone, Chief Technology Officer at Alphawave Semi and Professor of ECE at the University of Toronto, presented a talk on “Connectivity and a Chiplet Ecosystem for Sustainable AI Scaling.” He spoke of the benefits of chiplet technology—reduced cost, shorter time-to-market, and lower power consumption—that are paving the way for sustainable AI scaling. By enabling the seamless integration of dense logic, memory, and high-speed connectivity, chiplets fuel the demand for higher bandwidth both within and between packages. Specifically, low-latency inter-die communication and high-speed optical connectivity are essential to meet the performance needs of AI. Furthermore, he described how a robust ecosystem around chiplets is being built to support the flexible design of systems-in-package tailored to specific workloads, ultimately accelerating development and innovation.

Edith Beigné, Silicon Research Director at Meta Reality Labs, spoke on “AR/VR applications at Meta: deep dive into silicon challenges for AI.” Her presentation reviewed augmented reality and virtual reality applications and silicon challenges. Augmented reality is a set of technologies that will fundamentally change the way humans interact with the environment. It represents a merging of the physical and the digital worlds into a rich, context-aware, and accessible user interface delivered through a socially acceptable form factor such as eyeglasses. One of the biggest challenges in realizing a comprehensive AR and AI experience is the performance and form factor requiring new custom silicon. Innovations are mandatory to manage power consumption constraints and ensure both adequate battery life and a physically comfortable thermal envelope.

In addition to the excellent talks described above, the symposium included a poster session and panel discussion. Best poster awards were also presented to the best poster in each of the three poster session tracks. The details of the program are listed in the following link: https://www.zurich.ibm.com/thinklab/AIcomputesymposium.html

Speakers/committee; L to R: X. Zhang, R. Joshi, J. Han, K. Magraoui, A. Watanabe. A. Andreou, T. Gray, J. Park, R. Narayanaswamy, M. Ziegler, E. Beigné, A. Kumar, T. Carusone, J. Nasrullah, C. Chi, and A. Topol.

The IEEE Electron Devices Society (EDS) Neuromorphics Technical Committee is pleased to announce the successful conclusion of a Rump Session held on 11 March 2025 during EDTM 2025 in Hong Kong, dedicated to exploring the latest advances and future directions in neuromorphic computing technology. IEEE EDS VP of Technical Activities (New Initiatives) Merlyne de Souza gave the opening remarks and the event was chaired by Han Wang, chair of the EDS Neuromorphic Technical Committee. Other key organizers included Can Li from the University of Hong Kong and Jianshi Tang from Tsinghua University, both members of the EDS Neuromorphic Technical Committee. The event was also co-hosted by the University of Hong Kong Center for Advanced Semiconductors and Integrated Circuits. Moderated by Deep Jariwala (University of Pennsylvania), this dynamic forum drew around 170 participants and featured five distinguished panelists:

Neuromorphic computing—an interdisciplinary field inspired by the structure and function of biological neural systems—holds tremendous potential for revolutionizing fields from artificial intelligence machine learning to data processing and energy-efficient hardware design. This Rump Session served as an open forum for sharing insights, posing tough questions, and brainstorming solutions to the field’s most pressing challenges. Each of the five panelists also delivered a brief presentation, examining neuromorphic computing from the perspectives of materials, devices, architecture, and algorithmic innovations, and highlighting the key challenges and opportunities in this rapidly evolving domain. Subsequently, the panelists and moderator sat down to discuss the challenges facing neuromorphic computing as it moves from research to real-world applications. Their conversation centered on five key areas: materials, circuit architectures, algorithms, reliability, and commercialization.

Participants of the session from left to right: Deep Jariwala (moderator), Mario Lanza, Wei Zhang, Saptarshi Das, John P. Strachan, Shaodi Wang.

In terms of materials, the group focused on emerging devices (e.g., resistive RAM, ferroelectrics, MRAM, and 2D materials), emphasizing the need to overcome reliability and manufacturability hurdles while reducing power consumption. With regard to circuit architectures, they examined how analog and digital approaches could be integrated, explored the potential of 3D integration, and considered solutions based on existing silicon CMOS platforms. On the algorithmic front, the discussion highlighted the tension between hardware-driven algorithmic constraints and algorithm-driven hardware design, as well as the significant challenges posed by spiking neural networks. Concerning reliability, participants underscored the importance of robust testing protocols and the development of standardization frameworks to ensure that neuromorphic technologies can be scaled consistently. Lastly, when it comes to commercialization, the panel recognized the gap between academic prototypes and industrial-scale products, urging stronger collaborations among academia, industry, and government to facilitate the transition from lab to market.

Throughout the session, the panelists and audience members engaged in lively debates and interactive brainstorming, underscoring both the remarkable progress to date and the significant hurdles that still lie ahead. This collaborative dialogue showcased the commitment of IEEE EDS and HKU to advance the frontiers of electronics and semiconductor research, while also enabling interdisciplinary innovation in computing architectures and materials science.