Chapter News

Denver Chapter
During the past half year, the SSCS Denver Chapter hosted several technical seminars and a social event. In May 2004 Michael Rubin of Agilent Technologies presented “IC design solutions in a foundry environment,” an important topic especially given the concentration of fabless design houses in northern Colorado. Due to summer tapeout pressures encountered by the chapter officers, chapter activities resumed in September with a BBQ social at a local clubhouse. The following month, Ken Richardson of LSI Logic presented an informative tutorial on “Measurement, modeling, and simulation of high-speed transmission lines.” This was a particularly applicable seminar since many local companies in Fort Collins have active R&D efforts in developing high-speed serial data interfaces.
Our year ended with a seminar on the globalization of engineering and high-tech jobs, a topic that attracted participation from over one hundred people—the largest attendance since the chapter’s inception two years ago! Dr. Don Morris, recently retired from Agilent Technologies, gave a thoroughly insightful presentation on the controversial topic. He drew upon classical economic thought and provided powerful historical examples of high technology and international trade dating back many centuries in order to motivate the conclusion that the outsourcing of commoditized engineering activity to lower-cost geographies is merely an inevitable and natural economic evolution driven by the “cold, dead hand of Adam Smith.” Alluding to his experiences managing a design lab he created in Singapore, Dr. Morris also explained that the high-tech sector in Singapore was in deep fear of job outsourcing to even lower-cost geographies. The key to surviving through such economic trends is to embrace outsourcing whenever and wherever possible in order to enjoy cost advantages sooner than competitors, but continue to innovate new products, hence creating new activities to replace outsourced ones. On a personal level, this requires continual development of new skills that enable such innovations so as to maintain marketability.
The 2005 annual elections were also held in November with Dr. Alvin Loke elected as Chapter Chair, Dr. Don McGrath as Vice Chair, Tin Tin Wee as Secretary/Web master, and Bob Barnes as Treasurer.
We look forward to growing participation in upcoming seminars. Please visit our Web site at ewh.ieee.org/r5/denver/sscs/ for more information (including past presentation slides) about our chapter events.

Alvin Loke
Denver Chapter Vice Chair
alvin.loke@ieee.org

Tin Tin Wee
Denver Chapter Secretary/Web master
tintin.wee@ieee.org

ED/SSC Varna Chapter
The Technical University of Varna, Bulgaria, held a three-week summer school on CAD in electronics, funded primarily by the joint IEEE Solid-State Circuits and Electron Devices Chapter. There were lectures and practical training by faculty from the Technical Universities of both Varna and Sofia. The main topic was analog IC design, simulation, and layout using Pspice and Cadence software products. Of the sixteen in attendance, half were IEEE members.
In the fall of 2003 the Varna Chapter cosponsored two technical meetings. As a part of the Conference ET2003 (Electronic Engineering 2003) in Sozopol, whose primary sponsor was the TU of Sofia, more than 100 papers were presented in the sessions. As part of the anniversary conference of the Technical University of Gabrovo, there were over 90 papers presented in the sessions on electrical engineering, computer science and engineering, electronics, and communications.

Jordan Kolev
SSCS Bulgaria Chapter Chair
ikolev@ieeel.bg

Kansai Chapter
The Kansai Chapter held a technical seminar on 25 October in Kyoto, focusing on interconnects in terms of signal integrity in nanometer-scale designs. Two excellent speakers attracted an audience from across Japan, including 34 professionals and 12 students.
Toshiki Kanamoto from Renesas Technology Corporation provided a tutorial lecture on “Interconnect modeling technology for SoC design,” introducing the basics of timing analysis, interconnect modeling and extraction technologies. He also provided insights into the practical consideration of inductive parasitics in SoC design with the latest EDA tools.
Dr. Nishath Verghese from Cadence Design Systems dealt thoroughly with delay calculation for gate models that accurately accounted for long wires, crosstalk, ground bounce, temperature inversion, as well as process variability. The interplay of crosstalk and timing was covered in his presentation, “Accurate crosstalk and timing analysis of nanometer-scale digital ICs.”
Both talks were well organized, providing a good reference for experienced designers as well as motivating students towards innovative thesis work in the VLSI design field. Questions from the audience and answers by the lectures were very detailed and helped further understanding of the topics, which characterized the success of the seminar.

Makoto Nagata
Kansai Chapter Secretary
mnagata@ieee.org