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Have Your Read the Top Cited Articles?
The Journal Citation Report—2000
Science Edition points to the top 20 cited articles from the Journal
of Solid-State Circuits since JSSC’s inception. All have over
100 citations, that is, over 100 other peer-reviewed articles by authors
who knew to cite these documents fundamental to their work. The Journal
is ranked 17 out of 203 scientific journals for frequency of citations,
ranking higher than 13 journals that published more articles in 2002.
Two-thirds of the most frequently cited JSSC articles were published
prior to 1980. Although it may be true that it takes time to grow a quantity
of citations, half of most citations of JSSC articles are made
in the initial seven years after they first appear. Robert Dennard, lead
author of the most frequently cited paper, suggests that most progress
in the last twenty years consists of incremental advances, and seminal
breakthroughs are less characteristic of the field than in the 70s and
early 80s.
Eight
of the papers were developed from presentations originally made at conferences:
the 1988 article by Krummenacher and Loehl was developed from an ESSCIRC
Conference, the six articles published in December were developed from
ISSCC presentations, and Dennard’s article was an outgrowth of a presentation
originally made at IEDM.
Dennard’s article on MOS scaling, published in 1974, has
been cited about five times more often than most of the other top twenty
and three times more often the second most frequently cited article, a
paper on a low-power CMOS digital design by Anantha Chandrakasan et al.
See the attached article for more comments from Dennard, explaining the
genesis and impact of his paper, now almost thirty years old. Look for
more interviews with top-cited authors in future issues of the SSCS
Newsletter.
| IEEE
JOURNAL OF SOLID STATE CIRCUITS ARTICLES CITED 100 TIMES OR MORE |
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In chronological order with number of citations
listed first
|
Frequency
Cited
|
Title
|
Authors
|
Issue |
129
|
A precise four-quadrant multiplier
with subnanosecond response
|
Gilbert, B.
Tektronix,
Oregon, USA
|
Vol. SC-3,
No. 4
pp. 365-73,
Dec. 1968 |
128
|
Ion-implanted complementary MOS transistors
in low-voltage circuits
|
Swanson, R.M. ; Meindl, J.D., Stanford
University Stanford, CA, USA
|
Vol. SC-7,
No. 2
pp. 146-5,3
April, 1971 |
126
|
Integrated injection logic: a new approach
to LSI
|
Hart, K.; Slob, A.
Philips Research Labs Eindhoven, The Netherlands |
Vol. SC-7,
No .5
pp. 346-51, Oct. 1972 |
126
|
Merged-transistor logic (MTL)a
low-cost bipolar logic concept
|
Berger, H.H. ; Wiedmann, S.K.
IBM Labs, Boeblingen,
West Germany |
Vol.SC-7, No.5
pp. 340-6
Oct. 1972
|
593
|
Design of
ion-implanted MOSFETs with very small physical dimensions
|
Dennard, R.H.;
Gaensslen, F.H.; Yu, Hua-Nien; Rideout, V.L.; Bassous, E.; LeBlanc,
A.R.
IBM T.J. Watson Research Center
Yorktown Heights, NY, USA |
Vol.SC-9,
No.5
pp. 256-68, Oct. 1974
|
125
|
Characterization of surface
channel CCD
image arrays at low light levels
|
White, M.H.; Lampe, D.R.; Blaha,
F.C.; Mack, I.A. Westinghouse Electric Corp.
Baltimore, MD, USA |
Vol.SC-9, No.1
pp. 1-12
Feb. 1974
|
102
|
The monolithic
op amp: a tutorial study
|
Solomon, J.E.
National Semiconductor Corp.
Santa Clara, CA, USA |
Vol.SC-9,
No.6
pp. 314-32, Dec. 1974
|
148
|
All-MOS charge redistribution
analog-to-digital conversion techniques. |
McCreary, J.L.; Gray, P.R.
Univ. of California
Berkeley, CA, USA
|
Vol.SC-10, No.6
pp. 371-9,
Dec. 1975
|
122
|
Class E:
A new class of high-efficiency tuned single-ended switching power
amplifiers
|
Sokal, N.O.;
Sokal, A.D.
Design Automation Inc. Lexington, MA, USA
|
Vol.SC10,
No.3
pp. 168-76, June 1975
|
152
|
MOS-sampled data recursive
filters using switched-capacitor integrators |
Hosticka, B.J.; Brodersen, R.W.;
Gray, P.RUniv. of CaliforniaBerkeley, CA, USA |
Vol.SC-12, No.6 pp. 600-8 Dec.
1977
|
123
|
GaAs MESFET
logic with 4-GHz clock rate
|
Van Tuyl,
R.L.; Liechti, C.A.; Lee, R.E.; Gowen, E. Hewlett Packard Labs
Palo Alto, CA, USA |
Vol.SC-12,
No.5 pp. 485-96, Oct. 1977
|
101
|
A charge-oriented model for
MOS
transistor capacitances
|
Ward, D.E.; Dutton, R.W.
Integrated Circuits Lab., Stanford University Stanford, CA, USA |
Vol.SC-13, No.5 pp. 703-8,
Oct. 1978
|
100
|
Bipolar transistor
design for optimized power-delay logic circuits
|
Tang, D.D.;
Solomon, P.M.
IBM T.J. Watson Research Center
Yorktown Heights, NY, USA |
Vol.SC-14,
No.4
pp. 679-84
Aug. 1979
|
119
|
High-frequency CMOS continuous-time
filters
|
Khorramabadi, H.; Gray, P.R.
Univ. of California Berkeley, CA, USA |
Vol.SC-19, No.6
pp. 939-48 Dec. 1984 |
102
|
Characterization
and modeling of mismatch in MOS transistors for precision analog design
|
Lakshmikumar,
K.R.; Hadaway, R.A.; Copeland, M.A. Carleton University Ottawa, Ontario,
Canada |
Vol.SC-21,
No.6 pp.1057-66, Dec. 1986
|
105
|
BSIM: Berkeley short-channel
IGFET model
for MOS transistors
|
Sheu, B.J.; Scharfetter, D.L.;
Ko, P.-K.;
Jeng, M.-C.
Univ. of California Berkeley, CA, USA |
Vol.SC-22, No.4
pp. 558-66 Aug. 1987
|
151
|
An experimental
512-bit nonvolatile memory with ferroelectric storage cell
|
Evans, J.T.;
Womack, R. Krysalis Corp. Albuquerque, NM, USA |
Vol.23, No.5
pp. 1171-5 Oct. 1988
|
111
|
A 4-MHz CMOS continuous-time
filter with on-chip automatic tuning
|
Krummenacher, F.; Joehl, N.
ETH
Lausanne, Switzerland |
Vol.23, No.3
pp. 750-8 June 1988
|
156
|
Matching
properties of MOS transistors
|
Pelgrom, M.J.M.;
Duinmaijer, A.C.J.; Welbers, A.P.G.
Philips Res. Labs. Eindhoven, The Netherlands |
Vol.24, No.5
pp. 1433-9 Oct. 1989
|
103
|
High-speed CMOS circuit technique
|
Yuan, J.;
Svensson, C.
Linkoping University
Sweden |
Vol.24, No.1
pp. 62-70 Feb. 1989
|
206
|
Low-power
CMOS digital design
|
Chandrakasan, A.P.; Sheng,
S.; Brodersen, R.W.,
University of California
Berkeley, CA, USA
|
Vol.27, No.4
pp. 473-84
April 1992
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