JSSC Classic Paper: Scaling Enabled Moore’s Law

The 1974 classic paper on scaling MOS integrated circuits is far and away the most frequently cited article in the Journal of Solid-State Circuits. Written by R.H. Dennard, F.H. Gaensslen, Hwa-Nien Yu, V.L. Rideout, E. Bassous, and A.R. LeBlanc of the IBM T.J. Watson Research Center, Yorktown Heights, NY, the paper was titled “Design of ion-implanted MOSFETs with very small physical dimensions” and was published in JSSC in October of that year. This paper is frequently referenced because it contains the first publication of the unified set of principles for scaling MOS transistors and integrated circuits to increasingly smaller dimensions. It has been cited almost six hundred times, about three times more often than the second most frequently cited article, the 1992 “Low-power CMOS digital design” paper by Anantha Chandrakasan.

According to Robert Dennard, “The material had been presented two years earlier at the International Electron Devices meeting, but only a short abstract was published by IEDM in those days. All this scaling material was incorporated into a new paper that also presented design techniques for using the emerging ion-implantation technology to help in building small scaled-down MOS transistors. The idea of scaling all physical dimensions of a MOS device along with proportional changes of voltage and substrate doping is remarkably simple and concise, yet very powerful. It predicts significant improvement in speed and reduction of power consumption along with the profound cost advantage of fabricating many more transistors on each silicon chip.”

Scaling Enabled Moore’s Law

After publication of the paper, the concept of scaling MOS devices caught on very quickly and soon became the well-publicized business plan of some leading companies in the semiconductor industry. As Moore’s Law became recognized and popular, scaling down the key dimensions of integrated circuits by the square root of two in each generation was a vital part of making Moore’s Law work. These smaller MOS transistors were universally called “scaled” or “scaled-down” devices. Many new authors used these names and referred to the original “scaling” paper to introduce their field of work. A large number of papers were published to discuss limitations, extensions, and new techniques needed to fabricate the increasingly scaled devices.

How the Paper Came About

The scaling principles came out of a project started in IBM Research in 1970. Only eight years after publication, the article was featured in the weekly Institute for Scientific Information as a Citation Classic. Dennard said at that time, “We wanted to take advantage of potential advances in lithography techniques, particularly step-and-repeat optical projection or electron-beam pattern writing, which we felt could reduce typical dimensions used in integrated circuits from 5 microns to about 1 micron. Dale Critchlow was the leader and principal architect of these ideas. We knew that FETs exhibited a precipitous (and undesired) drop in the gate voltage required to switch them [i.e., the threshold voltage] when the source-drain spacing was reduced past a certain value, in those days about 4 microns.”

After further studies to confirm the theory by experiments and to understand the limits, they presented their work as described above. “Since the principles were first introduced,” Dennard says today, “scaling has been used to reduce integrated circuit dimensions by about 50 times and today’s computers are testaments to the results.”

Still Useful Today

Over the years the scaling principles have been extensively studied, improved, and generalized so that they are still useful today. “A major area of work is to try to understand how far they can be pushed by developing new materials, processes, and structures to overcome the inherent limits—where some problems that were negligible in the early days become dominant.” Dennard concludes, “As this work continues, undoubtedly the number of citations to the original source will also grow.”